Digital delay schematics

[Zero the hero]

Found a couple of schematics about digital delay (using dinamic ram) and digital echo.
I know that there are single chips that do the same... but I've got plenty of unused TTL chips and I dont know what to do with them...

http://www.armory.com/~rstevew/Public/SoundSynth/Reverb/ddl.htm

http://www.armory.com/~rstevew/Public/SoundSynth/Reverb/echodig1.gif

A question about the DRAM: I've got  many 256k dram, should they work with this schem (this one uses a single 64k chip)?
And another question: will this thing work?

[Maneco]

hi,
yes and yes...

to use the 41256,you'll have to ground the unused address pin...
the other works,but is noisy...

all the best

Maneco

[Zero the hero]

Thanks for the infos!
Noisy? I've seen another schematic of a circuit using Dram as storing area for delay. It used a HT8955 but I've never heard it. I'll go and find the datasheet of this chip (I've seen it at Mark Hammer's site sometime ago...).
Thanks again!

[Maneco]

Hi,
if you choose the "special function chip" way,then don´t waste your time with the ht8955,is expensive...just go and buy some pt2399 from steve daniels,www.smallbearelec.com,and build either the pt80 or the rebote delay 2...you'll have a nice delay without headaches...
all the best

Maneco

[Paul Perry (Frostwave)]

http://xtronics.com/memory/how_memory-works.htm
I don't know how DRAM memory works, but I know it requires some complex backup.. maybe this link will make it clearer!

[Boofhead]

DRAM doesn't create noise.  It's just storage and it stores the data perfectly.
Any noise comes from the surrounding analogue circuits and layout issues, design bugs can also cause noise.

The difference between DRAM and SRAM is you need to refresh DRAM, it's also a higher density RAM.

[Maneco]

what makes this design noisy is the resolution of the convertion process.

[Peter Snowberg]

Wow!  :shock: What a cool DRAM controller hack!

DRAM is usually a pain to work with because you have to feed it the address in two parts while supplying a complex clock sequence. You also have to access every row in the matrix every XX milliseconds or else the chip will forget the data. If you want a box that remembers loops when the power is off... go with static RAM.

Old PC motherboards would be a good source of chips.

By adding an octal latch like a 74HC374 or 574 for the output latch, you could use a 30 pin SIMM with each bit feeding the next to use the whole SIMM. If you clocked it at 2MHz, you would still have 8 seconds using a 1Meg SIMM, 2 seconds using a 256K, and 32 seconds using a 4Meg SIMM! Perhaps a more elegant solution would involve S/P and P/S shift registers on the inputs and outputs respectively with the DRAM access clocked 8 times slower than the shift registers. It would take less power, but more chips.

A 2MHz clock would give you great quality I would imagine. The circuit above has got to be running at a much lower frequency if it's using a 4164 for a buffer. Sony was talking about a next generation CD system that ran between 2 and 3MHz not that long ago.

Hmmm..... :twisted:

Take care,
-Peter

[Zero the hero]

TOOOOOO DIFFICULT (at least, for me)!!!!!!!!
The article about memory is very interesting.
I'll go and buy some BBD...