Help needed with RG's Sequencer...

[bobbletrox]

I'm really interested in building RG's 8-Step Sequencer from Geofex so I can try it out on a PWM, but I'm just curious as to whether I'm on the right track.  Here's a perf/schem I drew up to illustrate what I'm yackin' about (using trimpots)...

http://users.bigpond.net.au/styrowfoam/eightstep.gif

I'm only really interested in the Left>>Right sequence so the Schmitt Trigger is only connected to the count down pin (pink).  I filled in values for the oscillator using values from the PWM's Lfo, but what should the values of the resistor/diode combination and the cap between the inverters be?  Likewise with the resistor on the output...what should it's value be?  I'm guessing the 8 sequence trimmers could just be 500k.  This is RG's original schematic:

http://www.geofex.com/Article_Folders/udrand.htm

Am I on the right track with this?  It's my first forray with crazy logic.

[R.G.]

The cap between inverters and the diode/resistor are a MML (Mickey Mouse Logic) implementation of a one shot.

Here's how it works: The oscillator is going so slow that we can assume that there are DC conditions except at edges of the pulses up and down. Let's start with the oscillator output up. The resistor pulls the end of the cap connecting to the second inverter input up to +9, and the second inverter output is low. Then nothing happens until the oscillator output drops low again.

When the oscillator output goes low, the cap has 0V across it, and so it pulls the input of the second inverter low, which causes the output of the second inverter to go high - Houston, we have a high clock pulse.

But the input of the second inverter can't stay low because the resistor on its input starts charging the cap towards +9. At some time the resistor will charge the cap above the upper threshold voltage of the second inverter's input, and the inverter output will then go low, ending the clock pulse. The cap will continue to charge up until it is essentially at the +9 supply. Then nothing else happens until the oscillator goes high.

When the oscillator goes high, the cap has 9V across it, and the oscillator output shoves the cap *up* above the +9V power supply. This turns on the diode, which shunts the charge from the cap back into the +9V power supply, very quickly. The oscillator end of the cap is at +9V, and the inverter end is at +9 plus a diode drop. The resistor then ramps the cap back down to +9 on the inverter end. Neither of these matter to the second inverter, because its input is always above the lower voltage threshold, so its output stays low.

The RC/diode combination selects the positive going edge of the oscillator, and uses a fraction of the time it's going high to make a clock pulse. We get to choose how long that pulse is by choosing the RC values and knowing the voltage thresholds of the inverter input. This will come out to be some fraction or multiple of RC, because every RC circuit settles pretty much totally within five times RC if left alone. The smaller voltage limits of the difference between the input thresholds means that it will be a fraction of five RC times, probably around half or one. We can calculate that to a gnat's eyelash if we know all the voltages and such.

However, that doesn't matter to the counter all that much. The counter changes state on the positive going edge of its clock pulse, and doesn't care (within limits) when the negative going edge happens. So we just have to have the RC set the time of the clock pulse to be short compared to the fastest oscillator speed so that the RCdiode resets the cap correctly.

So - RC has to be much (defined in electronics as a ten to one ratio) shorter than the oscillator speed. With the fastest oscillator at 10 per second, that's a period of 0.1 seconds, so if RC is as short as 5 milliseconds ( a tenth of the half-cycle) we'll be just fine.

Picking R = 100K because that's a good value for a lot of CMOS input resistors, then t= R*C, C = t/R = (5e-3sec)/(0.1 E-6 ohms) = 50E-9 Farads (by the way, ohms times farads are seconds) or 50nF. With R=100K, C can be 50nF or less. 1nF would give a pulse of 100uS, which is a nice tidy value and C is smaller, so I'd use 100K and 0.001uF.

On the output end, you need a resistor that's big enough not to matter to the resistances in the trimmers. Make that 1M to 10M. The output cap needs to be big. Make that 100uF like the one the trimpots attach to.

The trimmers need to be comparable to the wah pot value. I'd start with 100K for them, but 500K certainly includes that. It's just that you may not have a lot of usable range.

[bobbletrox]

Thanks for that detailed description, RG!  

I updated the schematic with your suggestions, so it should be ready to build now;

http://users.bigpond.net.au/styrowfoam/eightstep.gif

I'm thinkin' of using a TLE2426 rail splitter for that pesky 4.5v.  The interesting thing about using this sequencer for a PWM is that there are enough spare inverters left on the 40106 to build it on the same chip.  Heck, there's enough inverters on the 40106 to build the sequencer, the PWM, and a second LFO.  A 3-way switch could be used to select between a "Seek-PWM", a flanger style effect, or a manual pulse width.  It'd probably need a ground plane and well filtered power supply to stop all that clicking getting into the audio though.  I don't know how you could fit 14 pots into a BB sized enclosure either.

[Arno van der Heijden]

How hard would it be to incorporate a switch for 6 or 4 steps only?
Is it possible to make it go up-down-up-down-....?

[bobbletrox]

How hard would it be to incorporate a switch for 6 or 4 steps only?
Is it possible to make it go up-down-up-down-....?

The Vanishing Point is probably more what you're after.  I leaned more towards RG's sequencer because it doesn't involve opamps and has a lower part count.

[R.G.]

I'm thinkin' of using a TLE2426 rail splitter for that pesky 4.5v.

As I posted some time back, you can also use an LM386 power amp with grounded inputs for a rail splitter. It's bigger (8 pin DIP instead of a TO-92) but much more readily available.

[Arno van der Heijden]

The Vanishing Point is probably more what you're after.  I leaned more towards RG's sequencer because it doesn't involve opamps and has a lower part count.

I've seen that one, but I understand this one a little better and I also like the lower parts count.
I was just wondering if there's an easy way to incorporate these things in this design.

[R.G.]

How hard would it be to incorporate a switch for 6 or 4 steps only?
Is it possible to make it go up-down-up-down-....?

It's not - in theory. The '193 is an up/down counter. All you have to do to make it do up/down is route the clock pulse to the count up or count down pin to change directions. The easy way to do that is to decode some condition of the 193 outputs and use that to toggle a flipflop to change the routing of the clock pulse. The 4051 is also usable as a decoder, so you could parallel the inputs of another 4051 to the existing one, but use the output of the 4051 to route a "1" to the toggle input of a 4013 flipflop on whichever output you like. The flipflop output Q and -Q outputs could enable the clock pulse into either the  Count up or Count down inputs. Likewise, the decoded output can be wired into the reset pin on the 193 and this will reset it to zero on any chosen output.

But about now one starts thinking - Hmmm... three chips for the basic counter, another three to add the U/D and variable number of steps option, that's six chips at $0.50 a chip... hey! ... I could afford a $2.00 PIC and get much fancier operations in a smaller PCB.

The hard logic implementation is easy to understand, easy to implement but not easy to modify.

It's a tradeoff.

[Arno van der Heijden]

But about now one starts thinking - Hmmm... three chips for the basic counter, another three to add the U/D and variable number of steps option, that's six chips at $0.50 a chip... hey! ... I could afford a $2.00 PIC and get much fancier operations in a smaller PCB.

Hmmm... yes but I'm not familiar with PIC's, don't have a device to program them, nor do I have knowledge of the program language used.
Moreover, I can get free samples of these logic chips from TI.

Makes it easy to pick a solution.....

[maximee]

It'd be interesting how many guys from this forum ordered TI samples to build R.G.'s sequencer this week

[Arno van der Heijden]

It'd be interesting how many guys from this forum ordered TI samples to build R.G.'s sequencer this week

I know I did!  :twisted:

[maximee]

I NEVER would  :lol:

[bobbletrox]

Oh yeah I forgot to ask...

A 1N4148 will do for the diode, won't it?

[R.G.]

Yes, a 1N4148 or 1N914 will do for the diode.[/quote]

[The Tone God]

The Vanishing Point is probably more what you're after.  I leaned more towards RG's sequencer because it doesn't involve opamps and has a lower part count.

Hey guys/gals. I thought I would give some insight as to my design reasonning with the VP.

The use of opamps and more parts did not occur because I like complex things in fact I'm a fan of the "KISS" methodolgy. One of the earlier VPs designs used inverter gates for the clocks very much like R.G. does in his circuit. I also used a few spare gates for the reset logic and audio so there were no opamps originally. Some noise issues occurred with using the gates for the audio portion as well as clocking so I went to the dual opamp setup for the audio. After that change was made there was still clock noise getting into the system from the harsh spikes created when the inverter gate LFO was switching states. I had a hard time eliminating the noise to what I considered a reasonable level so I went to a "softer" LFO using an opamp. By using the opamp LFO and watching my ground I was able to remove the noise nicely. I then implimented the reset logic using a spare opamp thus elminating the need for the inverter gate IC.

The only noise I get with my VP is when one stage is switching to a stage with an extremely different setting. I wouldn't really consider that noise as I would suspect other similar devices have the same problem.

I tried to give enough detail about the operation of the logic so others could impliment similar functions in other circuits. An example would be the bounce mode logic using the flip-flops which could be implimented in R.G.'s circuit.

Unlike R.G.s circuit I've included the filter section. His you need to build one which means more parts anyways. I don't know if R.G. actually built his or that was just theory on his part. I'm sure he can chime in to let us know if needed. I can say I've built the VP so I can confirm it works.

It should be pointed out the the VP is fairly flexible configuration wise. If you don't want the pattern mode leave out the parts for the second clock. If you don't want the bounce mode leave out the flip-flop. If you want to use it to control another circuit leave out the audio section. The VP can also be configured as a single stage phase shifter for psudo-vibrato or as a volume control for tremolo style sounds. Other things that can be done are listed at the end of the article.

I do have a VP2 on the design board with even more features, including more stages, but as I have other things going on and other effects I want to post it will be alittle while before I get that done.

I hope this helps out.

Andrew