Where can i find the PT2399 Chip?

[puretube]

that "new source" 36pin chip for external RAM looks from it`s data-sheet (which btw. isn`t very informative...) exactly like the PT2395 minus the lacking A8;

they write "M50915P compatible", but very probable mean:

"M50195P compatible";

anyone have some datasheet/application notes for that (old) Mitsubishi-chip???

[puretube]

finally have managed to find a direct import for the Princeton PT2395
- looks like even cheaper than those Chinese M*ts*bishi clones -

Peter: do you just use a 4013 to provide an A9/A10 adress and for "delaying" the reset accordingly?

[Peter Snowberg]

Peter: do you just use a 4013 to provide an A9/A10 adress and for "delaying" the reset accordingly?

Good news on the distributer!

My "scheme" is to increase the buffer by adding *width* and not *height* .

I do have a diagram drawn up that uses a pair of flip-flops to create a pseudo A9 from a latched and divided A8, but there is no easy way to know when the PT2395 is trying to source the row or the column so the best I could come up with would utilize only 1/2 of a 1 meg chip. This diagram also assumes that the PT2395 is refreshing at least 2X the minimum speed required by the memory. I still need to toss a chip on my logic analyzer to see the refresh method. If it uses self-refresh, that last speed requirement is no longer an issue.

I look at the PT2395 and weep because pin 40 is N/C and my mind thinks it should have been A9. Oh well.... at least there are plenty of 256k*4 chips out there.

What would the purpose be of delaying the reset? (is that just for clearing the whole DRAM at power-up?)


PS: Ton, I'll get back to you RE that PM ASAIC, or ASAP.

[puretube]

I thought "somebody" got to tell the address-counter, when to start at 0,
and how far to count (64k or 256k, for extended memory:512k or 1M)
and then reset to O and start counting all over.

The Holtek 8955 had an extra pin to select the kind of RAM used (64k or 256k), which was nothing other than a logic select (Hi or Lo) for "where" to reset the counter.
(This Holtek was/is(?) also interesting in the fact, that it had 2 clock OSCs: one for audio-sampling, and an independant one for delay-time!
Dunno if it even had SCFs linked to the audio-clock...).

Anyway: I`m not sure, how this reset is done in the PT2395:
there is a mysterious "Delay-select" box in the top-right corner of the data-sheet, which detects the levels on 3 "select" pins, to control the central "main control logic" block, which in turn is responsible for counting and so on...
It`s a little unclear to me, "how" the chip "knows", if it addresses a 64k or a 256k RAM (or an 512k or even 1M)concerning address-counter reset;
for those larger RAMs, the reset-the-counter-pulse should occur "later"
(i.e.: after 512/1024k), which I referred to as "delayed"...

Do I mis-interpret something?


edit: oops: just found out, the PT2395 in fact does have that memory-select pin(20), too...

[Peter Snowberg]

As far as I can tell, the reset line is only used to store a "blank" pattern in the buffer to eliminate a loud burst of static at power-up. It may also work by reducing the span of the "adaptive" part of the adaptive delta demodulator to zero. That would be a clean way to do things.

I would not be surprised at all if the address counter is left to be random, in fact it may be a LFSR based counter where the counting sequence is nothing like 1,2,3,4,5....

I'm sure the address counters just roll-over to zero so no reset is required for them. Selecting between 64K and 256K is simply a matter of running the A8 output through an AND gate with the 256K enable signal and then selecting the column address from either A9-A17 or from A8-A15.

As the address counter is only 18 bits wide, the PT2395 has no ideas about address spaces that are larger than 256K and therefore no idea how to refresh larger arrays if it uses an internal refresh counter.

[puretube]

noticed earlier today, that I need to refresh my memory on this subject a little...
:wink:

[Maneco]

to expand the memory of the pt2395 you have to parallel the ram chips and use the cas signal as a chip selector,driven by a counter...

[puretube]

...which would be "increasing the width" for e.g. a 256k*4, like Peter said, right?

[Peter Snowberg]

Interesting... I never thought of using a counter to select different chips.

My approach uses a single memory chip, a latch on the data lines, and one other (fairly) common 74HC or 74HCT part.