The case against drain trimmers in JFET/MOSFET circuits

[davebungo]

Hi,
before I start off on this one, I have nowhere to post a schematic so you will have to use your imagination and think of the typical generic JFET stage with Rd to V+, Rs to 0V and Rg to 0V ignoring DC blocking caps.  

I've seen quite a few circuits (esp. valve amp simulations) where a trimmer is fitted in place of Rd which is then adjusted to get roughly 4 or 5V at the drain (Vd).  If you consider that the gain of such stages is directly related to Rd and Rs (among other parameters) it seems a little imprecise as the gain of your stage will depend on the bias adjustment.

BTW the gain of such an amplifier is given by the following equation:
Av = -gm.rd.Rd/(rd+Rd+gm.rd.Rs) where gm is the small signal transconductance of the JFET.  If Rs is a significant value (more than say 100 ohms) then the expression simplifies to approx -Rd/Rs.  

So what is the alternative?

Well one alternative is to assume fixed values for Rd and Rs and adjust the DC bias VGS to achieve a given drain current (ID) which would place VD at a desired value say 5V.

The problem is that most FETs have a fairly variable range of VGS required for a given ID.  If you take a BF245A for example, it has a VGS(OFF) range of -0.3 to -1.5 i.e. a 5:1 ratio.  If we choose ID to be say 200uA then the range will probably be something like -0.15 to -1.2 or somewhere in that region.  So we could set Rs to provide 1.2V VS (or -1.2 VGS at 200uA i.e. 6K ohms, but what if the particular JFET needs -0.2V?  In this case we could make a potential divider to provide 1V at the gate i.e. VG so VGS would now become 1-1.2=-0.2 (as required).

So what I'm saying is fix Rd and Rs and ID to desired values assuming the worst case VGS you are likely to get in the range (this could be reduced by selecting individual JFETS) and then use a trimmer in the gate bias instead of in the drain.

This has concentrated on the JFET circuit but the MOSFET circuit can be treated in a similar way.

Any comments?

[aron]

What is the advantage in terms of ease or use when altering the gate resistor?

What are the typical values of the gate trimmer when doing this?

[seanm]

Interesting. If you have a sample schematic, I would be happy to host it. Just PM me.

[Dragonfly]

So what I'm saying is fix Rd and Rs and ID to desired values assuming the worst case VGS you are likely to get in the range (this could be reduced by selecting individual JFETS) and then use a trimmer in the gate bias instead of in the drain.

This has concentrated on the JFET circuit but the MOSFET circuit can be treated in a similar way.

Any comments?

i actually asked about this in a thread i just posted...wish i'd seen yours first.

my question "echoes" yours in that "wouldnt, since the gate-ground resistor typically determines bias in circuits, it make more sense to put your trim pot there?"

so i guess my thoughts might be correct.... ?

andy

[puretube]

free information sucks...

[aron]

For a while I was trying the voltage divider bias but for some reason I was having a very difficult time with it.

Even thought the drain method is crude, it works.

[davebungo]

What is the advantage in terms of ease or use when altering the gate resistor?

What are the typical values of the gate trimmer when doing this?

Well, firstly I'm going to read the pdf referred to in puretube's link; that looks really interesting and I will probably learn something from it.

The advantage of altering the gain resistor(s) is that Rd and Rs and Id can be left fixed and therefore the voltage gain of the circuit is predictable even though the bias required for the individual JFET isn't.

The amount of trim required just depends on the variance of VGS values for the device type, but there's no reason really to restrict it other than ensuring that you can't accidentally burn out a device by forward biasing its gate-source junction too heavily.  For the example I mentioned, I would probably use a 200K to +9V and a 100K trimmer to 0V giving an adjustment range for VG of 0 to 3V which should be more than adequate.

[R.G.]

Dave, your insight is correct. Getting predictable gains with JFETs does call for adjusting the gate bias for low voltages. If you have a lot of voltage to throw away, you can set up a biasing circuit that does fairly well for them with NO trimmers. Siliconix had an article on biasing JFETs with no trimmers on their web site at one time. I read it, thought about it, then decided like most analog circuit designers "Nah, not worth the trouble."

Two things make this possible.
1) enough voltage on the source to turn the JFET down to at least the drain current you want
and
2) JFETs with Vgsoff significantly lower than the power supply, which I guess is really a restatement of 1.

Most people here use the J201, the 2N5485, or other similar JFETs with low Vgsoff, in the 0.2 to 3.5V range. There's a reason for that, whether it's recognized or not.

That lets you turn them off with a modest voltage. The majority of JFETs have bigger Vgsoff, as big as 12V by casual memory. If you get a big Vgsoff, you can't turn it down to where you want it with a 9V supply, because you have to have the source at most of the power supply voltage to get the right back-bias. Fortunately we have low Vgsoff JFETs available, at least a few types.

But with a low-Vgsoff device, you can indeed use a trimmer on the gate. It's a bit more advantageous to use the trimpot across part of the supply as a voltage divider and then a high-value resistor to the gate instead of as a pull-down resistor to ground. This is the method I use in the MOSFET Boosters article.

You get a couple of advantages with the trimpot as a voltage divider. First, with a high-value resistor to the gate, the high value resistor is the signal load, and it remains effectively constant, so your input impedance does not rely on the bias setting, and remains high.

Second, the voltage divider point can be bypassed to ground. In these conditions, any noise from the bias resistors is shunted to ground, and you get lower noise from high resistor values for biasing. In bipolars, this same setup can be used; it's called "noiseless biasing" there.

[davebungo]

I think it's also worth mentioning that you could select JFETs from your own stock with lower VGS(OFF) values assuming you have some way of testing them (could be done in circuit).  

The advantage of a lower VGS(OFF) value is a larger potential VDS i.e. the JFET can swing further before hitting the end stops (which isn't far on a not-so-new PP3).  If VS is sitting at say 3V (because this happens to be the amount of negative bias required by the device for the operating current you have chosen), then you will only have 9-3=6V to play with.

In this case you are probably better off setting VD to be about 5.5 to 6V rather than the obilgatory 4.5V.  It is easy to overlook the fact that although the drain may be at half supply rail, the headroom in the other direction i.e. VDS can be limited by a large VS.  In the example given VDS would be about 1.5V, so any large output signals would be clipped on negative going peaks well before postive going ones.  It is worth bearing this in mind if you require a nice clean output.  So my advice is to measure VDS as well as VD when adjusting the bias.

One the other hand, perhaps bad asymetrical clipping sounds nice.  This is all very subjective at the end of the day, I'm just trying to illuminate things a little.

[davebungo]

The circuit shows an example of two BF245s (an 'A' and a 'B' to simulate the spread of VGS(OFF)).  These have been biased up with a 100K trimmer in the gate circuit.  The "best" case (simulated with a BF245A) with lowest VGS needs 550mV on the gate to provide 2mA into a 500 ohm Rs whereas the "worst" case (simulated by a BF245B) has the trimmer set to 0V.

For clarity, I haven't shown any decoupling caps or input/output connections.  The usual Rs bypass capacitor/variable resistor isn't shown either.  This would be used to increase the gain.  The gain as shown would be 1.5K/500 = 3 or about 9dB.  If you bypass Rs with just a capacitor, then the gain is more dependent on the gm of the device (roughly -gm.Rd).

Hope you find this useful/interesting.

Thanks to seanm for hosting the image for me.
:wink:

[Doug_H]

I'm late to the party here...

The inconsistent stage gain due to inconsistent drain biasing due to inconsistent JFET production spread is one of many limitations in trying to "emulate tubes" with JFETs, IMO. AFAIC, the problem is the use of the word "emulate", which I studiously avoided when I designed my meteor pedal a few yrs ago.  That was a case of "What would happen if...??" and I was pleased with the results, that's all.  The "E-word" has been thrown around a lot, esp wrt the ROG circuits, but I would never claim this kind of thing "emulates" tubes.  But they are nice sounding circuits and it's a fun approach to designing a pedal.

IMO, aside from being an interesting mental exercise (perhaps), I find "emulating tubes" with SS gear to be pretty much a dead end. The op amp based AC-30 sim is very complex, yet the clips don't sound near as close as I would expect to the real AC-30 clips he provided as a comparison, given the complexity of the circuit. (Yeah, I know... Clips...) In the end you usually end up with a horribly complex SS circuit to mimic the tube circuit. And most tube amp circuits are godawfully simple.

So instead of worrying about trying to make one thing sound like something else, I accept the notion that there are lot of different approaches for getting good sounds, using a lot of different gear. I.e., It's all good AFAIC... And if I want a "tube sound" I'll just build a piece of tube gear (which I do)...

Doug

[B Tremblay]

AFAIC, the problem is the use of the word "emulate", which I studiously avoided when I designed my meteor pedal a few yrs ago.  That was a case of "What would happen if...??" and I was pleased with the results, that's all.  The "E-word" has been thrown around a lot, esp wrt the ROG circuits, but I would never claim this kind of thing "emulates" tubes.  But they are nice sounding circuits and it's a fun approach to designing a pedal.

I'm with you 100% on this one, Doug.  All occurrences of that loaded word were recently removed from the 'Groove for exactly that reason.  Now we describe those nifty little circuits as "the ___ amp, adapted for use as a distortion stompbox."

[puretube]

glad to hear this from you guys - thanx - so I won`t spend a second afternoon on them FETs...

[davebungo]

But my point was nothing to do with any form of valve circuit emulation.  I just happened to mention that I often see them used in such circuits, but the points raised stand regardless of the application.

[Brian Marshall]

Well i actually make a production pedal that uses jfets with drain trimmers.  I attempted to convert it to gate biasing, but it wasnt working any better, infact it was worse... this was probably due to the fact that i was using mpf102's at the time, and their VGSoff can range anywhere from 3 to 8 volts or something like that.   they seemed to be getting out of their audio region before they biased.  It got to the point where i was going through 20+ to find one that worked... eventually i switched to 2n5458's.  they seem to have a much more consistent VGS off, and most bias with a fairly similar drain resistance.  with in 1 k ohms.

[puretube]

I found that CMOS inverters love me...  

related thread:


LINK EDITED...

[brett]

Hi.  I *LOVE* FETs.  Why?  1.  V high input impedance.  2. Tube-like distortion in some circuits.

Siliconix had an article on biasing JFETs with no trimmers on their web site at one time. I read it, thought about it, then decided like most analog circuit designers "Nah, not worth the trouble."

I've been thru this same process as RG.  The trade-off that you get from following Davebungo's schematic is that the input impedance is only 100k, whereas a FET with the gate grounded by a 1M resistor gives you about 1M.  Such a setup works works great as an input stage in many effects (e.g. in front of a 386 for a simple "Ruby" type amp or a signal probe, where the 386 otherwise has an input impedance of only 50k).

BTW, the Siliconix article mentioned by RG is AN102, titled "JFET Biasing Techniques", dated Mar 97.  Other useful articles re FETs include National application note AN-32, and Erno Borbely's areticles in Audio Electronics, around 1999, including "JFETS: The new Frontier, Part 1".

cheers

[davebungo]

Well i actually make a production pedal that uses jfets with drain trimmers.  I attempted to convert it to gate biasing, but it wasnt working any better, infact it was worse... this was probably due to the fact that i was using mpf102's at the time, and their VGSoff can range anywhere from 3 to 8 volts or something like that.   they seemed to be getting out of their audio region before they biased.  It got to the point where i was going through 20+ to find one that worked... eventually i switched to 2n5458's.  they seem to have a much more consistent VGS off, and most bias with a fairly similar drain resistance.  with in 1 k ohms.

With a possible VGSoff of 8V in the normal spread and assuming you're operating at a fairly low current to keep battery consumption down, you are in for a struggle no matter what you do.

[davebungo]

Hi.  I *LOVE* FETs.  Why?  1.  V high input impedance.  2. Tube-like distortion in some circuits.

Siliconix had an article on biasing JFETs with no trimmers on their web site at one time. I read it, thought about it, then decided like most analog circuit designers "Nah, not worth the trouble."

I've been thru this same process as RG.  The trade-off that you get from following Davebungo's schematic is that the input impedance is only 100k, whereas a FET with the gate grounded by a 1M resistor gives you about 1M.  Such a setup works works great as an input stage in many effects (e.g. in front of a 386 for a simple "Ruby" type amp or a signal probe, where the 386 otherwise has an input impedance of only 50k).

BTW, the Siliconix article mentioned by RG is AN102, titled "JFET Biasing Techniques", dated Mar 97.  Other useful articles re FETs include National application note AN-32, and Erno Borbely's areticles in Audio Electronics, around 1999, including "JFETS: The new Frontier, Part 1".

cheers

The input impedance is set by the resistor connected from the bias network to the gate (1Meg) in the example shown, the input would be connected to the gate - it's the same as the AMZ MOSFET boost  :wink:

[brett]

Oops! I missed the 1 meg resistors tieing the gates to the bias voltage dividers.  I'll try to look before I leap next time. :oops: