question for R.G. concerning footswitch logic ?

[donald stringer]

I have an sn74hc373n on the breadboard. I am planning to build the octal latch to use in a project. A minimalized version of yours. I have an 7805 supplying 5volts. OE to ground, q1 to an led. I am  working this with minamum parts first, then if I can at least get an led to light up I will take it the rest of the way. I am not using an 4049 to debounce it [just trying to toggle it by touching d1 to positive voltage. But so far have been unsuccesful. Could this be the the wrong chip? I know you have listed 74c373. but was hoping to use this one. As I said I know I have power but nothing is working  as of yet. Any pointers would be appreciated. I really appreciate your articles on switching with cmos but I have been putting this project on the backburner for a while but now though I am ready to build...........What would really be cool would be a switching project utilizing off the shelf radio shack components and thos relays they sell. I know they are not popular for this sort of hobby but maybe a nice project would come out of it, and they are a quick fix for a lot of people.Thanks ahead of time.

[R.G.]

Good, pertinent questions, Donald. I'll try to clear a few of them up.

I have an sn74hc373n on the breadboard. I am planning to build the octal latch to use in a project...  But so far have been unsuccesful. Could this be the the wrong chip? I know you have listed 74c373. but was hoping to use this one. As I said I know I have power but nothing is working as of yet.

The HC part will not work in the minimal circuit, for an obvious reason if you know where it's hidden in the datasheet, and also know to go look in the datasheet.

Logic chips are ...fast... in their operation - they have to be. The primary consideration in choosing one over another in the real engineering world is raw speed. They are so fast that the time it takes an electrical signal to travel the tiny distances across the chip from pin to pin matter a lot. Inside them, everything matters, from which transistor is next to which all the way to which one-micron signal wire is longer or has slightly more femtofarads of capacitance to ground.

Some input pins have a faster effect on the output pins than others. That is what is getting you in this case.

The '373 logic is a transparent latch. When the clock is high, the data on the "D" inputs flows through the chip directly to the outputs in a few nanoseconds. When the clock goes low, whatever data was valid at the D inputs when the clock dropped is held latched in the outputs.

But what if the data was not rock solid, but was changing when the clock dropped? They worry about that a lot in the logic world, because every piece of logic in the real engineering world is usually pushed right up to the hairy edge of not working at all under some conditions, so **exactly** when the data quits being validly latched is critical.

The data sheet specifies two things about the D inputs versus the negative going clock edge: setup time and hold time. The setup time is the amount of time in nanoseconds which it takes for the data at the D input to get to the input of the internal latch on the chip to be ready to latch. The hold time is the time after the clock drops that the data must remain in whatever state it was in so the internal latch can "grab" it properly and get the right result latched. If the D inputs violate either specification, the result is not guaranteed, which in data-sheet-speak means "it ain't a-gonna work all the time" which is far worse than simply failing.

So now we're down the nub of the problem. In this circuit, the D inputs are the same as the clock, minus that silly eight input diode OR gate that converts any D input to a clock. The clock rises a few nanoseconds after the D input (time to get through that diode and the unconscionably long inch or so of copper trace) and the D input drops before the clock does, by the same amount. In this case, the D setup time we are asking the chip to work with is some positive amount of time, and the D hold time is **negative** because the D input drops before the clock.

How can this ever work?

It works because the hold time for the 74C373 is negative. That is, by the time the setup time from data to clock is satisfied, the internal capacitances in the chip are holding the data, and hold it up long enough that if the D input drops, the clock will still latch what the D input **was** for a few nanoseconds.

This does not work for the HC family, where the hold time is positive. For HC373s, the data must hold still for 50-150ns after the clock drops to guarantee that the correct value will be latched.

I started to put the actual numbers for the C373 in here, so I went off looking for datasheets, and found an interesting thing. I've looked that number up before, as you might guess, so I was surprised to find that no manufacturer of the 74C373 that still makes them lists a hold time for the part. They apparently just quietly editted out this oddity sometime in the last decade. Sure enough, hold time is shown prominently as one of the things that is important in the switching speeds diagrams, but there is no spec for tHOLD in the speeds listings.

All that is a long winded way of saying - it won't work as shown with anything except a real 74C373 - not a 74HC373 or a 74HCT373.

But there is hope. I ran into this same question a ways back and came up with some circuit mods that let the D inputs stay good long enough to work with HC parts. I'll have to dig out the circuit but it involves using an RC on each D input to hold the data up for a while.

What would really be cool would be a switching project utilizing off the shelf radio shack components and thos relays they sell. I know they are not popular for this sort of hobby but maybe a nice project would come out of it, and they are a quick fix for a lot of people.

You're probably right. Let me see what I can do.

[donald stringer]

As usual a very thorough answer.I have been thinking about this project for a while so I can wait a little longer. I want to work through this a little at a time anyway in order to understand whats happening. Dont you live in austin or close to it. My mother two sisters and sister in law live in taylor and tyler texas. I really enjoy my visit every time I go out there.I will be looking forward to your post and happy easter.

[R.G.]

Thanks! Yes, I live near Austin. Austin does have its attractions. And happy Easter to you and yours.

[scratch]

R.G. - Could we use a Schmitt trigger instead of a regular inverter? to get around the issue w/ the hold time on the 74HC373?

[R.G.]

I didn't get a chance to draw this up yet, but the way it works is to use a diode to allow positive signals to each D input, a capacitor to ground to hold the D input up for a microsecond or so, and a resistor to ground to discharge that input so it's ready for another signal in several microseconds. The clock gets a diode from every signal input to its own parallel RC to ground. The C's are all the same, and the R on the clock is smaller than the R on the D inputs. That way, the clock signal runs below the logic threshold before the signal on the D inputs. So the D input that has been triggered is held above the logic threshold for a bit longer than the clock, and is still valid when the clock has run down.

Ain't MML (Mickey Mouse Logic) fun??

Actually, you need schmitt triggers on the switched to do a good debounce anyway. But they won't help with the timing. As I remember, the D an clock inputs are schmitt trigger inputs anyway, so again, no help. You have to externally supply the timing.

That's why the 74C part is so good. It has a useful quirk.

[scratch]

Got it!

Even with the Schmitt trigger to hold the input up, we still feed the clock signal from it so it doesn't buy us much ... More diodes, caps and resistors, it will mean a lot more connections, more 'real estate' ...