Question about logic on CD4013

[filterazonatie]

I'm trying to understand the way the dual-d flip flop cmos works. As I understand it, with -Q tied to D, and S and R to ground, a rising-transient on the clock will trigger the logic flip flop from Q to -Q.

If a high logic is appled to S, Q will turn on and -Q will turn off.

If a low logic is then applied to S, will Q and -Q return to their previous state?

For reference, the application is to control RG's remote bypass relays. I want to have a switch that toggles between Relay A and B, and another switch that can bypass both. Say Delay 1 and Delay 2, and a second bypass switch.

[The Tone God]

If a low logic is then applied to S, will Q and -Q return to their previous state?

No. The pulse on the S pin forces the flip-flop to the appropriate statet. It does not have any memory as it is just a logic gate so it cannot remember what its previous state was.

I make use of the S/R pins in The Original Vanishing Point for these very functions. Might be any interesting read for you.

Andrew

[rubberlips]

just a quick one on top of what tone god said,
The S & R pins are generally used  as preset logic for when you power the chip up, so that  Q or -Q are at a predefined state at powerup.
However they're also used in counters, so you could use the output of one to control another to do what you want

Pete

[filterazonatie]

Okay... :? so let me see if I have this right.

If I am using the 4013 for the typical flip-flop logic (pulses to clock, -Q tied to Data, Q and -Q used as flip flop) and then apply a positive voltage to R, it will default to the Reset state regardless of what state it was in. If I *remove* the positive voltage from R, will it stay in the reset state  -or- will Q return to the D state? THAT'S the part where I'm confused.

Thanks guys!

[The Tone God]

If I *remove* the positive voltage from R, will it stay in the reset state  -or- will Q return to the D state? THAT'S the part where I'm confused.

D is only read when a clock pulse is sent therefore removing the signal from R without a clock pulse following afterwards will cause the 4013 to remain in the forced state. As stated earlier the 4013 is just a gate with no memory so it has no idea what it's previous state was to be able to return to it.

Andrew