questions for mu-amp, and jfet biasing gurus

[idiot savant]

so, im *trying* to teach myself a bit about fet biasing, ive spent the last few days going through the archives and scouring over every pdf and article i could find, i have found the stuff on RG's site, and AMZ particularly interesting.

Looking at the mu amp, the top jfet is biased by the 2 1m resistors, which half the voltage at the gate,  and shares it's source with the drain of the lower jfet. i understand that the bottom jet is the amplifier, and the top one is a source follower helping to move the load, however, when i was skimming through a few places, looking for examples of simple gain stages, i came across tim escobedos snippets.  The SyRuPP really caught my eye, as well as his Duende.

I realize that in his configuration, that the top fet is a constant current source, but how does it mantain bias, and follow the source of the lower fet without any 1m biasing resistors, like in Orman's mu amp, or the SRPP in RG's minibooster article. similarly the lower fet doesn't have a 1m to ground from the gate, or is that what the 1m pot(potential divider) is for, and if so wouldn't that make the effective impedance drop as more gain is used? Furthermore(SyRuPP), what purpose does the trimmer from the source of the top jfet to the drain of the bottom jfet. I see something similar in RG's article, isolating the source from the drain with a 1k resistor. I ask this because i really want to learn about biasing fets and making some simple gain stages to start designing, and to help me understand the process. this ype of configuration shows up all over Tim's snippets, in the cinnabar, tytewadd, and kechi wah.

Am I just thinking about this completely wrong or what?

BTW, thankyou to anyone who bothered to read all that :lol:

[idiot savant]

sorry, i guess i should post links so people know what the heck im talking about.... :oops:

http://www.geocities.com/tpe123/folkurban/fuzz/snippets.html
http://www.geofex.com/Article_Folders/foolwfets/foolwfets.htm
http://www.geofex.com/Article_Folders/modmuamp/modmuamp.htm
http://www.muzique.com/amz/mini.htm


thanks in advance for any replies.

[aron]

for $12....

http://www.muzique.com/amproj.htm

[davebungo]

In the SyRuPP, the bias for Q1 is provided by the trim-pot.  With the circuit in its quiescent state with a current ID flowing through both Q1 and Q2, the source of Q1 will be higher in potential than the gate.  

i.e. Q1 VGS = -ID * Rtrimpot.  

Having said this, with an N channel JFET, an appreciable current will flow with VGS = 0 and some of the snippets do have the JFET biased in this way.  It is usual though to bias VGS negative - this is why you often see a source resistor which is used as described to generate a voltage on the source which is higher than the voltage on the gate (hence VGS is usually -ve).

[idiot savant]

thanks dave, i think ive read a few of your posts on this subject in my searching, what you said makes alot of sense to me, so with the top fet acting as a constant current source, the gate of the lower fet is biased at vgs=0, so the source resistor is used to set the current from drain to source positive with relation to the gate, whew, i think that makes sense to me, i really need to bone up on my math... there's alot more to it than i thought :oops:

[puretube]

not to confuse anybody, but some more related linx:
http://www.tubecad.com/articles_2002/SRPP_Deconstructed/index.html

http://diystompboxes.com/sboxforum/viewtopic.php?t=29414

[idiot savant]

thanks puretube, i've been reading those nuts&volts documents for a day or two, they def. shed some light on the subject for me.

much appreciated!!!

[davebungo]

so with the top fet acting as a constant current source, the gate of the lower fet is biased at vgs=0, so the source resistor is used to set the current from drain to source positive with relation to the gate, whew, i think that makes sense to me, i really need to bone up on my math... there's alot more to it than i thought :oops:

The lower FET is biased with VGS = -ID * 22K so VGS will be -ve.  It is important to differentiate between VG which will be 0, VS which will be +ve and VGS which is the relative difference and will be -ve.  

Also, (not trying to be picky but it may help clarify things for you) it is useful to use the accepted conventions to avoid confusing yourself when describing voltages and currents in amplifier circuits:

Use capital letters to describe the DC quiescent operating conditions i.e. VG, VS, VD, VGS, VDS, ID etc. etc.

Use lower case to describe the small signal variations about the quiescent conditions or, more commonly described, the operating point i.e. id, vgs, vds

For absolute levels of small signal voltages and currents (i.e. not relative to the operating point) use Vgs, Id etc.

It is very easy to get confused otherwise!

[idiot savant]

Also, (not trying to be picky but it may help clarify things for you) it is useful to use the accepted conventions to avoid confusing yourself when describing voltages and currents in amplifier circuits:

I really appreciate all the help, I have been building for awhile now, and I am just now getting to the hows and whys of the way circuits work. Without a place like this I dont think I would even be able to begin to understand. I really have no *proper* electrical knowledge so you have really helped me a great deal, just reading datasheets all day isn't really enough to cement something in my mind, you know. It's a great deal better for me being able to bounce these ideas around with people that know what they're talking about.  

Now off to the breadboard.......