Does Escobedo's PWM really PWM?

[thehallofshields]

Okay, so I'm just a journeyman and I've been trying to think of ways to manipulate the Duty-Cycle of perfect 50% Squares from CMOS stuffs.

I had the idea of messing with the Bias of a Schmitt Trigger, but I tried it in a couple simulations and it didn't work.
Then I rediscovered Tim Escobedo's PWM Fuzz and realized it was doing just that: 2 Schmitt Trigger Stages, with the second Input leaking DC to Ground.



1.) Does it even work as intended?
2.) Does the Duty Cycle go from 50%-0% as the pot shunts the signal to ground?
3.) Is the Duty-Cycle kind of consistent across different Audio frequency ranges?
4.) Is there a better way to do this?

[Freppo]

1. Yes it does work.

The small input cap combined with the pulldown resistor/pot makes a 'positive edge to negative going pulse' function.
The pulsewidth depends on both the input cap and the resistor. Don't ask me exactly how it works...

If you put the resistor (or pot) to V+ insted, you get a negative edge to positive going pulse.
I used this trick in my CMOS phaser, but at very high frequencies.

2. I guess so. Never played around with that circuit. It could probably use a fixed resistor to ground in series with the pot to set the minimum pulsewidth.
3. No, not really. But for guitar it works ok. For a pure square wave oscillator the pulsewidth control would only work optimally at a certain frequency.
4. Yes, but it depends on what you need it for. To control the pulsewidth of an oscillator there are better ways that works over a much larger range using diodes.

[thehallofshields]

So the Voltage at the Schmitt Trigger's Gate (Pin 3) does actually drop between 4.5V and 0V. -Cool.

I was really hoping that with a Pot between 9V and 0V (and some series resistance) I could get a range of like 20%-80%.
It's not working in simulations so I'm very confused.

I can't imagine how Pin 2's Output Cap or any HPF action would contribute.

[hymenoptera]

I think it just stores a charge. Eventually it discharges to ground through the Width pot, the time it takes depending on the width pot settings. At some point it crosses the threshold for the next input's Schmidt Trigger and flips polarity, ending that pulse. The cap and pot are establishing the time constant for the width of each pulse.

Or I could be totally wrong. Still trying to wrap my head around all of this digital stuff. It's all pretty new to me

[anotherjim]

The RC is a differentiator. It produces a saw-like output waveform that reverses direction from each level change of an incoming square/pulse wave. The curved slope decay time back to the zero crossing of the saw shape is directly set by the R & C values. When fed to either a comparator or a Schmitt trigger, the resulting output is a pulse wave with a pulse width corresponding to when during the saw wave slope the detection threshold voltage is crossed.

As the image shows, an input frequency with a faster period than the RC time defeats the differentiator effect, so a fixed RC time tends to give consistently sounding results over only about 2 octaves.

[thehallofshields]

Awesome! This is exactly what I was looking for.

Differentiator feeding a Schmitt Trigger; that's plenty to sink my teeth into.
2 Octaves is an acceptable range, but I wish there was some magic-bullet for Duty-Cycle control.

[thehallofshields]

Okay last question:

Is this setup going to work with Discrete Schmitt Triggers, Opamp Schmitt Triggers, CMOS Inverters arranged as Schmitt Triggers?

[anotherjim]

Anything that switches according to a defined input level will work, so long as the polarity is worked out right. Any Schmitt trigger of course, but also any logic gate - they all have a switching threshold.

Bear in mind the negative part of the wave -  it really is going negative below 0v. CMOS has input diodes and they should act to clamp the input no more than a diode drop negative and the Escobedo circuit is relying on this. With other circuits you may need to put a reverse diode across the RC resistor to clamp out the negative cycle.

[thehallofshields]

Bear in mind the negative part of the wave -  it really is going negative below 0v.

That's a little mind boggling, but I guess it kind of makes sense if the capacitor is storing charge...

Would the Diode be there to prevent reverse-polarity damage or just for stable operation?

[hymenoptera]

That's a little mind boggling, but I guess it kind of makes sense if the capacitor is storing charge...

And the output of the LM386, too. It goes negative half the time, and plenty of current available. You can probably destroy some components with those chip amps.

Would the Diode be there to prevent reverse-polarity damage or just for stable operation

I think it's all for protection. Standard fare in well designed ICs I think.

[anotherjim]

MOS devices have the diodes for free - they form as part of the process, "parasitic diodes". They are normally reverse biased so don't affect normal operation. A MOS device is full of P-N junctions between the substrate (base silicon) and the circuit elements. Sometimes they form P-N-P-N which is a SCR or Thyristor. If a pin voltage exceeds VSS or VDD, a parasitic thyristor can be triggered causing the logic to "latch-up" until power is switched off and on. When experimenting with CMOS logic, you can expect to experience this sooner or later.
In the RC network, if the capacitor is large, the negative pulse can beat the internal diodes and cause a latch-up.

To explain the appearance of negative voltages, if the input to the C has switched up to +9v, then the C charges via the R until there is the full +9v stored across the plates of the C. When the input switches back to 0v, what happens to the 9v charge? It's still there, and if the end of the C that was +9 is now 0, then the other end must become -9v! It will be -9v until it discharges via the R back to 0v. It MUST be allowed to discharge the negative cycle or it won't be able to react again to the next positive cycle, so we can't block it with a series diode.

A reverse parallel diode, either added by us or built into the device, will not only prevent the chip seeing the full (and damaging) -9v, but also rapidly discharge the negative cycle whatever the variable R is set at.
Speaking of damage, what about the discharge current? The Escobedo circuit, like countless others, ignores the high peak currents generated. They get away with it because a CMOS output has high resistance compared to other technologies. Note that the first inverter is driving the RC- not the 386. From 30-50ohm for a device intended to handle drive currents or 100-200ohm for most general logic. Excessive current will still be experienced briefly, but not for long enough to cause heating damage, so it gets away with it.
What about the current in the protection diode? This CAN be damaging - permanently. If we're worried about this, we could fit a series resistor to the chip input pin - say 1k - that won't affect the timing or input level thresholds noticeably but will limit the diode current - protect the protection!