Different voltage divider configuration for Rats

[80k]

I noticed the Vref on GGG's Rodent schematic is quite a bit different than the original Rat. I also noticed that the Rat configurations have changed over the many different versions. For instance the GGG schematic has 10k resistors going to V+ and ground, and a 47uF electrolytic to ground. The original RAT has 100k resistors and a 1uF capacitor going to ground. I've also seen 33k resistors and a 47uF electrolytic to ground on another version.

I was wondering what the reasons for these different configurations are, and is there a reason to choose one over the other? I played around with it, but didn't notice a difference in sound.

Thanks!

[80k]

After reading a bit on the subject and reading This Geofex article, it seems to me that going down in resistance on the divider would reduce the effect that the circuit's load on the middle point would affect the voltage. So is choosing the resistor size in this case purely a compromise between power consumption and accuracy of reference voltage? In other words, good engineering practice would ask that you use just enough current to stay within, say a reasonable range around your desired Vref?

In this case, it seems to me that the GGG schematic may be concerned with sag and feels it's worthwhile increasing power consumption? And in this case, what is the effect of using a higher capacitor value to ground at that point?

Hope I'm understanding this issue better! Thanks!

[R.G.]

After reading a bit on the subject and reading This Geofex article, it seems to me that going down in resistance on the divider would reduce the effect that the circuit's load on the middle point would affect the voltage.

That is true.

So is choosing the resistor size in this case purely a compromise between power consumption and accuracy of reference voltage? In other words, good engineering practice would ask that you use just enough current to stay within, say a reasonable range around your desired Vref?

It depends. Good engineering practice is very much a process of deciding what matters and what doesn't.

There are some side effects to the impedance of the bias voltage. One is that everything connected to it is both mixed in the node and feeds into the various inputs which are biased there. In standard analog engineering, this is something to be eliminated totally. In pedal effects, it could conceivably add some useful resonances and/or feedback depending on what sound you're trying to get; or, given the easter-egging that is the standard "design" practice these days in boutique pedals, it may be stumbled upon and found interesting. This is one of those things that easter-eggers would bring up as a reason that trained designers can't design good effects.   

Or it may be that the extra current used by 10K resistors is not significant; 100K resistors  use 9V/200K=45uA, where 10Ks would use 450uA. Neither of these are too worrisome in terms of battery life. Maybe if you're trying to save the planet by using 400uA less it's a big deal, but that sounds to me much more like advertising than a real step in planet-saving.

The trained designers need to remember that "unwanted" results are often what is wanted in pedals, and the easter-eggers need to realize that they are wandering around a very large field looking for gold nuggets under rocks. 

In this case, it seems to me that the GGG schematic may be concerned with sag and feels it's worthwhile increasing power consumption? And in this case, what is the effect of using a higher capacitor value to ground at that point?

It's always fun to try to divine the thoughts of the designer by their component choices. However, that is a task that has many pitfalls. In many cases a designer of whatever stripe simply whips in whatever has worked most reliably for them before if a given section of circuit is not perceived as critical. Maybe whomever drew the GGG schematic just had an excess of 10Ks or just likes 10Ks. Maybe they instead *wanted* a 47uF cap there for other reasons in the circuit and didn't want to wait for a 47uF/0.5M time delay (which is 5*47E-6*0.5E6 = 117s, nearly two minutes) for the Vbias to settle to its final value.

[80k]

R.G.
Thanks very much for your insight. It does seem like it is not necessary to overthink it, but to rather try different values and see what works best.