JFET 101

[Le québécois]

These day's I have play with JFET to understand them......... but failed!

I use this simple sheme and starting resistance value (Kd and Ks) are from Tillman jfet preamp so Kd = 6.8k and Ks = 2.2k and Jfet is J201

http://www.till.com/articles/GuitarPreamp/index.html
V+ ------- Kd -----+ output +------Drain ------- source ----- Ks ------ ground
                                                             |
                                                           gate
                                                             |
                                                             |------------------ 3 Meg -------- ground
                                                       Guitar in


Under this condition, there is a little overdrive with strong guitar picking. My goal was to stop that overdrive and maintain clean signal all the way so I decide to put a 500k trimpot wired as a variable resistor at Kd position and start to measure the voltage at the output and also at the source resistor. This way was my attempt to figure out how this thing work..... So here are the limits that I have found  when Kd vary from 0 to 500 k :

Gain                   Kd            Vd            Vs
0                   8.8ohm       8.4            0.76
<1                   2.2k           7.65            0.76
±1                   3.3k           7.25            0.76                   ------------about unity gain
>1                   204k           1.37            0.75
hard clipping    272k      0.63            0.62

Gain is my impression from A/B switching while playing 
Vg is always 0 because in this case, this is how it is design

My only conclusions are 1) when we decrease Vd we have more gain and 2) when Ks is below 10 ohm there is no output and above 272k it's also sound very bad.
For 1) I have no clue and it's probably because I still don't now what matter for output (current or volt) and why is it so.
For 2) My other reading tell me that maybe a so low Ks affect Vgs to a to positive value when I pick on my guitar. Vgs should be at 0 or negative but never bigger than 0.6v.
Finally what I want out of this circuit is a mini boost (slightly more than unity) plus a high drive capacity (buffered signal) mounted on board directly out of my guitar. Oh... and what about battery draining optimization I don't want to open my guitar every gig to change the battery!

Can someone help me understand?
I'm not afraid of equations but sometime oversimplification may also help.

[BubbaFet]

You should add input and output coupling capacitors.
Remember, coupling caps block DC, and allow AC signals to pass.
Also, it is difficult to use a digital multimeter to evaluate AC signals...
an oscilloscope really helps.

I'd recommend using a 800 ohm to 1K source resistor as a pretty generic value for a J201,
and a 4K to 5K drain resistor will get you a gain of 2 to 3. Use a drain output coupling cap
of about 4.7uF, input cap of 0.047uF.

[R.G.]

The channel of the JFET is a semiconductor resistor. If you ignore the gate, it acts exactly like the resistor it is. This resistance is the specified "Rds on" in the datasheet. Things get slippery when you start thinking about the gate.

The gate is a sheet of diode junction lying over the drain-source channel. If you reverse bias that gate-channel diode area, inside the channel, it sweeps the electrons and holes out of a certain area close to the gate. The bigger the reverse voltage, the more of the channel that is blocked off and not able to conduct. In effect, reverse biasing the gate squeezes the channel closed just like a garden hose being squeezed closed by you standing on it. There is some voltage from gate to channel which will close off the channel entirely, forcing the current to drop to zero. This is exactly what happens when you squeeze a garden hose completely closed: nothing flows. The voltage which cuts off the current flow is called Vgsoff, and that's in the datasheet.

If you let a current flow down the drain-source channel resistor, there is a voltage drop along the channel. If you short the gate to the source, then the voltage betwen the gate and the drain end of the channel is bigger than the voltage between the gate and source end of the channel. That means that the voltage  through the channel itself can pinch off the current flow in the channel. It is in effect, its own current limiter. This current limit is called Idss, the current (I) flowing from drain to source with the gate shorted to the source. This is a value you find on the JFET datasheet. It's the biggest current the JFET can pass under normal conditions.

So let's set up a JFET. We use a power supply Vp, connected through a drain resistor Kd, the JFET, and a source resistor Ks. We'll leave the gate open for a minute. What happens? The JFET looks like a low resistor of value Rdson, and a current flows equal to Vp divided by the sum of the resistances, Kd+Rdson+Ks.

If we now tie the gate to the source, The JFET will only limit the current flowing if the current across the Rdson is greater than Idss. If it's not, the JFET does nothing but conduct. If Kd and Ks let enough current flow so the JFET reaches Idss, the JFET acts like a current limiting diode, and in fact some JFETs are sold for exactly this. But if we let Idss run, there is nothing left for the JFET to amplify with. We need to limit the current to less than Idss.

So we connect the gate not to the source, but to the ground end of the source resistor. We want a current to flow through the Kd and Ks which is less than Idss, and which leave some voltage across both Kd and the JFET so it can amplify. The voltage across the Ks adds to the voltage dropped in the JFET, and helps turn off the channel by making the channel be at a higher voltage because of the current flowing through it. The voltage across the Ks can never be as much as Vgsoff, because that would let no current flow, and that would reduce the voltage on Ks, and let more current flow. It's a negative feedback setup, and the JFET will settle down with the voltage across Ks being less than Vgsoff. Notice that since no current flows in the gate, it can also be tied to ground with a big resistor, and nothing else changes.

So - increasing Ks turns the JFET more off, making less current flow, but the current can never be zero when biased this way. Also, the current can never be bigger than Idss. This is the answer to some of your questions: changing Ks changes the current flowing through the JFET, and this changes whether the thing is biased properly to amplify or not. Bigger Ks turns it more off.

The JFET has some gain. This is expressed as a "transconductance"; the amount the channel current changes per volt of change of gate voltage. This used to be called "mho", the reverse of ohms, but it's now called a "Siemen" after the man. One Siemen is one ampere per volt of change; most jfets have gains of a few milllisiemen, or a few milliamperes per volt of gate change.

The transconductance sets how much the current in the channel will change for a gate change. The current change goes through the Kd and Ks resistors. If Ks could be zero for AC signals (like by using a great big capacitor to force it's AC voltage to be zero) then the voltage gain from gate to drain is the transconductance times the Kd drain resistance.

This only works if there is some voltage across both the JFET and the Kd resistor to change, so it helps if there are a few volts across each one. We also need a volt or two of DC across Ks to keep the gate properly set up for DC.

If we un-bypass the Ks, then the Ks voltage varies with signal too. The long and short of it is that gain drops to no more than Kd/Ks if Ks is unbypassed.

You'll notice that your voltage across Ks was always close to 0.76V. That's where this particular JFET balances its Vgs and the current through Ks. A different JFET will probably balance at a slightly different voltage.

You notice that the bigger Kd, the more voltage that's dropped across it. That makes sense, because the current through Kd is set and fixed almost rock solid by the Ks and Vgs in the source circuit. The drain is letting through an almost constant current. The gain goes up as Kd increases, from that gain = transconductance * Kd stuff or the gain=Kd/Ks stuff, depending on whether you bypass Ks or not.

Down to your questions:

1) when we decrease Vd we have more gain

This is correct, because you are increasing gain=transconductance *kd and gain=Kd/ks. Notice that it's increasing Kd that's doing the work. Decreasing Vd is just what happens when you make that resistor bigger.

2) when Ks is below 10 ohm there is no output

That's because with Ks so low, the gate is effectively shorted to the source, and only a constant current equal to about Idss, or whatever the drain resistor Kd lets flow. There's nothing left to vary, so no signal amplification can take place. Ks must be big enough to get Vs enough off of ground to back the drain current down from Idss to have some control of the channel current.

and above 272k it's also sound very bad.

This is because the Kd is so big that it's eaten up all the available voltage. Again the JFET can't change its drain-source voltage, so it can't amplfy. It causes massive distortion and probably dead-zone sound where you have to hit it really hard to hear anything. Kd can't be made too big, Ks can't be made too small, or things will not work.

Finally what I want out of this circuit is a mini boost (slightly more than unity) plus a high drive capacity (buffered signal) mounted on board directly out of my guitar.

That is good - because it is quite difficult to get high gains out of a JFET in circuits like this.

I would approach this by varying Ks and Kd to get about 0.5 to 1.0V on Vs (for the J201 you have; it will be different for other JFETs). Then pick a Kd which will leave about 3.5-4V on Vd. If I calculate correctly, that makes the current in the 2.2K Ks be I = 0.76V/2200 = 345uA. For Vd = 4V, the Kd is going to be Kd = (9v-4v)/345uA = 14.5K. Call it 14K or 15K, which are standard values. The gain will be at most 15K/2.2K = 6.8. That may be too much gain for you. You can then back the gain down by changing only Kd to a smaller value. You should hit unity gain about 2.2K to 4.3K, depending on a number of other variables.

what about battery draining optimization I don't want to open my guitar every gig to change the battery!

The J201 has an Idss of 0.2 to 1ma, 200uA to 1000uA. That's all the circuit could even theoretically pull. As I sketched out, it will be something like 100uA to 500uA depending on the individual J201 you get. 500uA is half a milliampere. A typical 9V battery is usually 200 to 450ma-Hr, so you can expect battery life of 400 to 900 hours if you turn off the battery when you're not using the guitar, perhaps with a fancy switching jack on the guitar. If you leave it on all the time, 400 hours is 400/24 = 16.6days and it'll run down in a couple of weeks to a month or so.

[BubbaFet]

Ohh... and what RG says! 

[PRR]

R.G. explains at length.

But what jumps out at me:

> 0      8.4
> <1     7.65
> ±1     7.25  
> >1     1.37  

The source resistor and the FET are in a "fight", a "tug-rope contest".

0.6V across the drain resistor and 7.65V across the FET is not a fair fight.

7.6V across the drain resistor and 0.62V across the FET is not a fair fight.

Dog versus elephant. Elephant versus dog. Either way is unfair.

""Generally"" an amplifier will be set up so the output node (the drain, collector, plate) is about half-way up the supply voltage. Fender tube amp: 300V supply, 200V at plate. E-H LPB (clean boost), 9V supply, 3V-6V at collector.

Since signal swings both ways, and ideally we don't use more power voltage than we need, this half-way zone is an optimum.

In pedals we don't need a whole Volt of signal yet use 9V batteries because they are handy. So you may not need to be right in the center. Indeed you got "output" with just 0.62V across the FET, because that's enough for even a hot guitar signal.

However you may find that small change of temperature or battery voltage will throw that 1.37V down to 0.7V, slam the drain into the source, extreme distortion on any signal.

With source and output capacitor, this plan should have significant gain with drain at 3V-6V.

> what about battery draining optimization

Like any simple amplifier problem. Select your plate/drain resistor similar to your load impedance, a bit lower. Since guitar-cable loads are mostly over 50K, a 22K resistor is a good value. Now adjust your source resistor until the drain sits "about half", say 3V to 6V on a fresh 9V battery.

If there's 4 or 5 Volts across the 22K resistor, it pulls about 0.2mA. A cheap 9V batt will carry 0.2mA for many many concerts.

{EDIT: 15K will work essentially the same; use what's handy.}

[Le québécois]

Happy new year

I spent time again with my JFET while trying to understand your answers. Although I now have a working minibooster + buffer (thank to all of you) I'm still confused. 

let see if this is correct :
If I place 15 k for the drains resistor and 2.2 k at the source, Imax will be 15000+2200+Rdson (apparently never more than 150 ohm on my data sheet so ignored in this case) then Imax should be 9v / 17200  = 523 uA. This value is correct since it's not higher than 1ma (limit of the Jfet).

Now, when I use my multimeter I measure 0.48v across Ks : The current is therefore 0.48 / 2200 = 218 uA.  Since Is = Id I can know calculate the voltage drop across the drain resistor --- 218uA * 15000 = 3.27 V.  Since V+ is 9 V I'm suppose to read 9v - 3.27v or 5.7V  at the drain of the Jfet and in this case at the output.  When I measure it, this work very well I have 5.6v.
This series of calculation have also work for 7 combinations of Kd and Ks that I have utilise and were Imax is in all case about 0.95 mA

Example : Kd = 987 ohm and Ks = 8110 ohm ---- 9v / 9100 = 0.98mA
                Kd = 8100 ohm and Ks = 1197 ohm   ----  9v / 9300 = 0.97mA
*** Yes I've measure the exact resistance of each little beast... This is also were I've concluded that Rdson is not changing anything since my calculation are working without taking it into account****

Here are my problems : 
1) Without a DMM, I'm unable to predict what will be Vs but as seen above with this value all the calculation become easy. What I'm I missing here?

2) I'm unable to have Vs more than 1v (even with 470k as the source resistor!). Is this were biasing the gate at higher voltage should start to be use?

3) Aside what should be increase to have more headroom? and If the gate is at 0v am I loosing all the negative portion of my guitar sinewave since it can't go below ground .... Or maybe it can??

[PRR]

> If I place 15 k for the drains resistor and 2.2 k at the source, Imax will be 15000+2200+Rdson

That's the absolute maximum current it could pull, with the FET FULLY-on.

From this point, the FET could go less-on, but it can't go more-on.

Audio swings _both_ ways. But FETs (and BJTs and tubes) only swing one way.

Our work-around is to adjust ("bias") the FET to be "half on", actually half-on compared to the load (drain) resistor.

With JFETs and tubes, we do this with a drain/cathode resistor.

A triode tube has a fairly simple relation between cathode resistor and operating resistance. A 12AX7 tube with a 1.5K cathode resistor acts-like (100*1.5K)+60K or about 200K, When used with a 100K plate resistor, the plate sits near 2/3rd of supply voltage, can swing from there up almost to the supply voltage and down near 1/3rd of supply voltage. (Tubes do not swing very close to zero volts; they do not turn-ON well.)

FETs are trickier.

> I'm suppose to read 9v - 3.27v or 5.7V at the drain of the Jfet... I have 5.6v.

That is a good operating point. From 5.6V you can swing up to almost 9V (about 3V peak positive signal) and down to nearly 1V (over 4V peak negative signal).

Notice that the current is "about half" of the MAXimum current with the FET full-ON: 218uA and 523uA.

When I see a strange circuit, tube or transistor, with simple resistor-loaded amplifier stages, I can estimate the power supply demand quickly. It CAN'T pull more current than V/R (where V is the supply voltage and R is all the resistance in series with the device, and usually the cathode/source resistor is too small to matter). It "probably" pulls "about half" of that.

> Without a DMM

How are you measuring voltages? (Do you mean oscilloscope?)

> I'm unable to have Vs more than 1v

If this voltage is more than "Vgs(off)", the JFET is "off". Vgs(off) or VTO is on the datasheet:
http://www.fairchildsemi.com/ds/MM%2FMMBFJ201.pdf  -page 2

For the J201, Vgs(off) will always be between 0.3V and 1.5V.

"Off" is infinitely small; the actual spec is 10nA (a very-very small current but can be measured).

> unable to have Vs more than 1v (even with 470k as the source resistor!)

1V in 470K is 2uA, 2,000nA.

Try NO actual source resistor, just your DMM. It is probably a 10 Meg input. 1V in 10 Meg is 100nA. More than the test-spec, but very-very small. I'd guess you get 1.1V. Using math we might extrapolate 1.2V at 10nA. This is within the 0.3V to 1.5V spec on the data-sheet.

With a 1.2V Vgs(off) part you will never get more than 1.2V in a self-bias connection.

And you don't really need more.

> it can't go below ground .... Or maybe it can??

Sure it can. The INput is not limited by the amplifier's supply voltage.

Try it. Put a 100K safety-resistor in series with a 9V battery. Connect it Gate to Ground, read the voltage on the Gate. One way, it will go right down to Negative 8.99V. The other way, it will only go up to +0.6V (a little more if the source resistor is large and "follows" the gate voltage up). (Without resistances, the Gate _current_ would rise to infinity and melt the gate; 8V lost in 100K is under 0.1mA, and J201 won't melt with 50mA gate current.)

Observe what happens to the Source voltage when you apply huge inputs. Try smaller inputs: a 1.5V battery, or a voltage-divider to give 0.1V positive and negative.