bias on jfet phaser circuit

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Hi,

I'm working on a jfet phaser on my breadboard ,a regular phaser circuit (like the maestro or the MXR phase 90 ) .

i just changed the LFO ,  it's made with 2 AOP in a classic square/triangle LFO (I'm only using the triangle output)

the "phase sound" is here , I can hear it but not as clean as It'd must be. I have a big "plop" and the .

I thinks I 've an issue with Jfets and their baising. I looked at few schematic close to mine and I can see there's a trimmer to put a bias voltage (via a  resistor) on the jfet gates with the lfo output.

Could someone explain more about that bias ? (I made some research but I didn't find something really helpfull)

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a tinny bump