Understanding the curious biasing of the "JFET"

[boogietone]

The EA Tremolo uses a JFET to couple the LFO to the audio circuit (c.f., http://tinyurl.com/3oawnst) The JFET changes the output transistor's emitter resistance in time with the oscillator. This increases and decreases the current through the BJT and the collector resistor and thus the output voltage seen at the collector. What is not clear is how the JFET is biased. The JFETs specified (2N5457s or J201s) are N-channel and according to what I understand require a negative voltage at the gate with respect to the source to 1) be reverse biased at the gate junction and 2) be able to have a usable depletion affect the on channel between the source and drain. I do not see how a negative voltage is possible at the gate. The swings of the oscillator should be between 0 and some positive value. The depth pot just sets the overall magnitude of the swing and with the 68k resistor in the GGG schematic never even gets to 0V (unless the oscillator hits cut-off). Since the JFETs source is grounded, there seems to be no way for Vgs to be negative. What gives? Is this a case were positive Vgs is in fact used?

[R.G.]

That struck me too when I was messing with the layout I did for it.

A JFET is as low resistance as it gets when Vgs = 0. Moving it more positive does not cause a lower resistance. However, it does act like a diode and conduct to the channel when it's forward biased. At the time I presumed that it was just driving the thing off for the negative going half of the LFO signal.

But it strikes me now that the JFET gate diode may be clamping the signal at the gate to ground. A diode clamp can force an incoming AC signal to be clamped to a voltage (usually ground). They were called "DC restorers" back in television days. I'm thinking this may actually clamp the top of the incoming AC LFO signal to ground, giving most of the signal below ground. It would be interesting to scope it and see if there's a DC shift.

[ORK]

Isn`t the modulating voltage at the gate vs. source 0.0V plus/minus half the LFO amplitude due to C4?
And do we know if the jfet characteristic curve in the first quadrant when in the ohmic region is being mirrored in the third quadrant?

[R.G.]

Isn`t the modulating voltage at the gate vs. source 0.0V plus/minus half the LFO amplitude due to C4?

That was my original thought, until I considered that the LFO voltage is a number of volts, and would forward bias the gate-channel. Without the diode nature of the gate-channel in a JFET, it would certainly be the case. The gate-channel junction sets up a voltage clamping situation of some sort. I don't know how effective the clamping is for this set of conditions.

And do we know if the jfet characteristic curve in the first quadrant when in the ohmic region is being mirrored in the third quadrant?

Interesting question, and maybe. Many JFETs are symmetrical in that the drain and source are interchangeable. I'll have to think about that one. A quick simulation runs shows it does not, but then you have to be really careful extapolating from a simulator for non-normal conditions.

The sim run does show the clamping effect when the signal into the gate is AC coupled. I think this is what's happening.

[boogietone]

I am glad to know that I was not hallucinating this "problem." My scope is a signal analyzer VST in Cubase. It is not the best by any means and there may be some artifacts from the AD conversion though I use a reasonably high quality Firestudio interface. I have looked at the gate signal and it is more or less symmetric for some middle of the range rates though it is not a pure sine wave. At at least one extreme rate setting, the waveform does get distorted. I suspect that this gives this circuit its characteristic sound.

If the gate was being clamped to ground on some portion of the wave, I would think that it would show some clipping like we see in a clipper distortion circuit. I have no idea how to measure the DC level at the output of a LFO. It may be possible to get some idea through Cubase but I have yet to see how. My DMM's response time is to slow to obtain any useful reading. Using it, I can only get an AC voltage at the gate WRT the source for the faster rates of from .4 to .7 V AC. At slow rates, a reading is not possible. The LFO seems to run from maybe 2 Hz to 8 Hz. I can try to capture some data from Cubase and post it.

I likely have a misunderstanding of this principle, but would the DC level (or better said average AC voltage) of the gate not be "bootstrapped" up to that of the LFO's collector DC voltage, which would necessarily be positive? There is nothing else biasing it up, down, or sideways. There cannot be any DC current running through what looks to be the forward biased gate-channel/source diode. There is no place for it to come from. From a DC point of view, would the gate not be considered floating and thus move to the DC level on the other side of the LFO coupling cap or would the N-P channel diode voltage drop between gate and source figure in to it?

I have tried sims with spice, but I am not sure that I have appropriate parameters for the transistors.

[mac]

I dont know if it's of interest but I remember that I had trouble biasing it long ago. MPF102 needed a small resistor at the source to work properly. BF245A worked fine. And 2sk117 not so well but better than mpf102.

mac

[R.G.]

I am glad to know that I was not hallucinating this "problem."

I think it's real. I believe the positive going peak of the LFO waveform does get clamped to ground by the gate-channel diode.

If the gate was being clamped to ground on some portion of the wave, I would think that it would show some clipping like we see in a clipper distortion circuit.

"Clamped" is probably too strong a word. In the EA trem, the LFO is fed to the gate through some resistors to ground. The source is grounded, and the gate-source is a diode to ground, in operation. It only acts like a FET when the gate-source is reverse biased. Forward biased, it looks like a high-resistance diode. Starting at power up, both the gate and drain are at 0Vdc, as they're both capacitor blocked. There is signal on the drain, but it's always at 0Vdc. When the LFO goes negative, the gate is pulled below the (grounded) source, and the JFET turns more off. When the LFO reverses and goes positive, it is forced positive with respect to the grounded source, so the gate conducts current into the source. That current has to come from somewhere, and in this case it comes off the capacitor leading to the LFO transistor's collector. That capacitor charges more negative on the JFET side because current from it is conducted to ground. When the LFO reverses, the gate-source diode turns off, and so the capacitor keeps the more negative charge that it had, and discharges it a little through the string of resistors to ground. Until it has time (i.e. t = RC) to discharge the negative voltage it got from the gate conducting, the DC on the gate is now a little negative. Unless the resistors can discharge that cap to ground before the LFO swings positive again, the next cycle of the LFO signal pumps it more negative again.

The gate-source diode junction always "clamps" the positive-going side of the LFO signal to ground when it's most positive, so the capacitor charges up more negative on the JFET side, and reaches an equalibrium when the pump up each cycle is discharged down by the resistances on the gate to ground. This has the effect of forcing the LFO signal as seen at the JFET gate to have a most-positive peak of one diode drop forward, which was called "clamped to ground" back in the day. It's probably not distorted by this, as there is little current flow when this happens in the long term case.

From a DC point of view, would the gate not be considered floating and thus move to the DC level on the other side of the LFO coupling cap or would the N-P channel diode voltage drop between gate and source figure in to it?

From a DC point of view, the gate is grounded by the resistor divider and "depth" pot. But since the LFO voltage is volts big, every positive going movement makes the gate-source diode turn on, pumping charge out of the coupling cap, and making the JFET side of the LFO cap more DC-negative.

This is the same mechanism that makes tube amps go into blocking distortion on big signals that make the grid positive with respect to the cathode, by the way - one way conduction.

[PRR]

Without reviewing R.G.'s comments:

> JFET .... increases and decreases the current through the BJT

No. BJT DC current is fixed (almost 1mA).

BJT stage gain has two extremes:
roughly-
4K7/1K2 or 4 (when right side of C3 is open)
4K7/120 or 40 (when right side of C3 is short-to-ground)

> JFETs ...require a negative voltage at the gate with respect to the source to 1) be reverse biased at the gate junction and 2) be able to have a usable depletion effect the on channel

What happens if the gate goes positive? You have gate current. If not large, no harm is done. And you have even-better channel conductance.

> I do not see how a negative voltage is possible at the gate.

Simple AC coupling. As ORK says.  Yes, collector of Q3 swings +0.2V to +6V. This is passed through C4 to a string of resistors returned to ground. The _DC_ voltage on this resistor string will BE zero volts DC, and the wobble signal will swing up and down from there. +3V to -3V.

That's ignoring that pesky gate. It pulls-down easier than it pulls-up. However there is enough series resistance in R7 to avoid charge-pumping and large asymmetry.

> with the 68k resistor in the GGG schematic never even gets to 0V

We just proved it swings -around- zero V DC.

Voltage at the top of R7 swings perhaps +3V to -3V. Voltage at top of pot R13 swings about +2V to -2V. Voltage at bottom of pot R13 swings about +0.5V to -0.5V.

The FET is "on" for gate near zero and "off" before -1.5V (for J201: -0.3V to -1.5V). The "on" resistance is OTOO 300 ohms. It does seem that a low-Vgs(off) J201 would still have large variation with "Depth" full-down. (It is possible the LFO swing is not as large as 6V p-p.)

> I have no idea how to measure the DC level at the output of a LFO.

Run a 1Meg resistor to a low-leakage 10uFd cap to ground. The voltage on the cap will eventually (>>10 seconds) be the average DC voltage. (Down 10% because your 10Meg DVM loads the 1Meg filter resistor.)

> this circuit its characteristic sound.

Another aspect is that the "linear" zone of a JFET channel is 30mV-300mV wide, and varies with gate voltage. For typical guitar level, there will be some distortion over part of the LFO swing. That's true for many of the more-cherished tremolos, including vacuum-tube grid-bias trem.

[PRR]

> Many JFETs are symmetrical in that the drain and source are interchangeable.

Nearly all common JFETs, for all audio purposes, S and D are arbitrary.

But you are wise to doubt the model on this. Many BJT models are off-kilter in the "abnormal" quadrants (as-if Ebers and Moll never lived).

> I do not see how a negative voltage is possible at the gate.

I can "see" it. If you don't, maybe my vision is bad? Pictures would help.

Ask the idiot assistant. I happened to have the EA LFO already modeled, and it wobbled fine. Bit over 6V p-p at the collector. I had been modeling the cold-start build-up; you see the first cycle is a bit of a wam-bam (many phase-shift LFOs are worse), then it settles nice. (In this trem the LFO is always-on so it hardly matters; in-amplifier trem LFOs are sometimes started/stopped "live" so start-up is an issue.)

I added the coupling cap, pot-string, and a JFET gate. You see that the first wam-bam has the pot-string well positive but 120K to gate diode bleeds the DC quick.

Rather than muck with audio, I applied a small DC voltage through a resistor to the JFET channel. The varying DC voltage implies the JFET channel resistance. We see it pulls down to about 200 ohms and goes very high. (In the full trem the extremes are limited by 180 and 1K2 resistors.) If Depth were reduced, the variation would be less.

[boogietone]

Thanks for all of the feedback. This will take some cogitating.

[ORK]

PRR: how about a small varying negative voltage on the drain? ("third quadrant")

[PRR]

> how about a small varying negative voltage on the drain? ("third quadrant")

SPICE models are semi-trustworthy in the "normal" quadrant, but the "abnormal" quads may be totally bogus.

EDIT: I'm getting suspiciously symmetrical traces even at high level. I suspect the 3rd quad is not modeled too well. Also the JFET model I have is scaled to a higher gate turn-off than the ones specified for the EA.

If you want "Truth", drop $3 of parts on breadboard; not a heavy investment.