Wave Forming block inside MN3101/2

[Thomeeque]

 Hello guys,

please, does anybody know how is this block implemented, how does it's circuitry look?



According to Igor's (Valentinych) post in EM3207 thread it seems that inclusion of this block could improve performance of MN3xxx BBD driven by clock signals based on direct 1:2 divider (e.g. 4013 in Electric Mistress) outputs.

Please note, this is not about clock signal buffering - for understanding of what Wave Forming block does* please read Igor's post.

Thank you, T.

* At least I believe that Wave Forming block is responsible for that

[Nasse]

I have seen discrete clock circuit or two for such use or such features, back then when TDA1022 was popular. Maybe some application notes did exist (philips?)? I´m quite busy until next week, can not go trough some papers that are buried

[Thomeeque]

I have seen discrete clock circuit or two for such use or such features, back then when TDA1022 was popular. Maybe some application notes did exist (philips?)? I´m quite busy until next week, can not go trough some papers that are buried

Hmm, could it be something like this



(looks like divider + waveforming integrated together)?

Directly from TDA1022 datasheet thanks a lot, Nasse! T.

[Valentinych]

Tomas, there are simple.
But today is already too late – almost midnight, I will answer tomorrow.

[Valentinych]

I don't know how formed impulses in MN310x. but I can tell, how to obtain the desired wave shape in a makeshift device.

If the MOSFET inverter will square wave, the output will have the same momentum, but reverse polarity, which edge will nearly match the fronts of the input pulse.
But if the inverter put integrating RC-chain, the fronts of the input pulses are integrated, and lose a rectangular form. The inverter is switched with a little delay, the amount of which depends on the time constant RC-chain. Output impulse will be detained for a short time, but its duration will remain almost unchanged. In the figure shown in the top three charts.

We need to slightly reduce the pulse duration. To do this, add parallel R diode. Now rising edge input impulse will be integrated, and falling edge remains rectangular. On this inverter switches with delay only on the rising edge. Pulse duration decreases latency on the rising edge. The figure is the fourth schedule.
Now again invert this momentum, and we get what we need for CP1! Of course, the last inverter need to collect two parallel inverters from the 4049.
The same operation will do for the momentum of the second phase of the management of BBD.



We need to reduce the pulse duration at time t = 100 ns.
We will consider the capacity of RC-circuit equal 20 pF. This is the input capacity of each inverter 4049. This means from external capacity, you can choose.
Then the resistance RC-circuit is: R = t/C = 10^-7/(2 * 10^-11) = 5000 Ohms. The nearest size – 5,1 kOhms.
If necessary, time can be adjusted by modifying the Tdead value R from 1 kOhms to 10 kOhms. In my view, the optimal delay is ~ 50 ns. With R = 2,4 -2,7 kOhms.

[Thomeeque]

 I see! That's just brilliant, Igor, thanks a lot!

On my EM3207 all I need to do is to replace two wire jumpers between 4013 divider and 4049 buffer by these RD pairs, easy enough to make me try it one day..

..but not today, today I'm going to see RED HOT CHILI PEPPERS LIVE: I'M WITH YOU - whoo whoo

I'll report back then, cheers! T.