JET characteristics that make for a good variable resistor

[boogietone]

JETs are notoriously variable on their own in terms of property consistency due to the manufacturing process involved. That being said:

What makes one JFET, or JFET type, a better candidate over another for use as a variable resistor?

Is one channel type, N vs. P, "better?" N-channel types are more discussed in general than P. The ones recommended for use in a Phase 90 are an example.  However, I am currently trying a P channel (2n3820) as resistors and they seems easier to bias into the ohmic region for a positive powered circuit, when the voltages around the component are close to ground, at least. The variability in my batch and potential matching needs of the circuit are a bit much, though. Are their any techniques to remove that variability from the equation.

Are their any recommendations for specific N- and P-channel parts for this use?

[R.G.]

The best thing you can do is to get a moderate Vgsoff device, with Vgsoff of 3-5V, then use drain-gate feedback to linearize it.

See the schemo of the Phase 45 for one method of linearizing. Takes two resistors and one cap.

JFETs distort as variable resistors when the signal voltage approaches the Vgsoff value. So big values of Vgsoff make the most linear ones. But that also means you have to use a BIG voltage change to change the resistance. Linearizing with resistors drops the sensitivity to control voltage about half as well. So  you run out of volts if you're powering from 9Vdc. Something like 3-5 volts of Vgsoff is about all you can do in a 9V pedal unless you upvert, invert, or otherwise extend the voltage for control.

The usual suspects for phaser JFETs work: 2SK30, 2N5292, 2N5485, etc. J201 has a remarkably low Vgsoff and is not the best choice for a VCR JFET.

[boogietone]

Thanks for the comments.

This is likely a fools errand - tried and discarded already in the long past - but the idea is to replace the two resistors to ground in the LFO circuit of the EA Tremolo with 2200 ohm resistors in series with P-channel JFETs both controlled by a voltage off of the power supply. I have tried it and it does work albeit as a strong function of the specific JFETs selected. The reason for the 2200 resistor between ground and the JFET is that this is the minimum resistance (plus whatever the Rds(ON) is) that supports oscillation. Replacing both resistors allows for both a faster and slower rate from the LFO. The choice of P-channel JFETs was because I did not see how to bias a N-channel device to any significant negative Vgs due to the 2200 ohm source resistor. It seemed easier to just use P-channel and work with a gate bias arrangement of Vgs from a simple voltage divider off of the nominal +9 power supply. I did start trying the linearizing technique mentioned. I had seen it before but not understood how it worked until now. I have not done everything yet with this yet.

The purpose, mentioned in a previous post, is to be able to sync to an external LFO so a VCR is needed.

I also have a boatload of data I collected that show the variability of the 2n3820 I am currently working with. Working from the JFET matcher circuit at geofex (http://www.geofex.com/article_folders/fetmatch/fetmatch.htm), I breadboarded a spaghetti of leads and a 12 position rotary switch to allow me to determine the Vgs vs R curve for all 97 of them. I will post the data shortly. It may be of interest.

[boogietone]

For what it is worth, here is a plot of the data I collected. The opamp was 1/2 a TL072. Power was from a 1-spot.



It is possibly notable that there are two curve types. One is significantly more log-linear than the other.

The initial JFETs that I tried in the LFO circuit mentioned above were just randomly selected. They were both in the middle of this profile but were not "matched." Using two JFETs with "matched" profiles and the largest available Vgs swing gave a wider controllable range of LFO frequencies.

One question I have about this data is whether or not it is really useful for the use I am considering because the triode region of a JFET is supposed to be in the region where Vds is below the pinch-off voltage, which I would think is less than 4.7V. Do I have this correct?

[R.G.]

That is a beautiful job of data-gathering. My compliments!

It is possibly notable that there are two curve types. One is significantly more log-linear than the other.

It's very notable! I suspect that those two types came from either two batches from the same maker separated by a lot of time, or two different manufacturers. National Semiconductor used to note on their datasheets (and Fairchild may still note) things like "sourced from process #57", which I took to mean "We use the #57 diffusion line, and sets of temperatures/timings that produce this, and it pretty much mostly matches the datasheet". But none of them specify action in the triode/resistive region that I know of. Well, maybe. There used to be a company supplying JFETs with imbedded resistors specifically for voltage controlled resistor use. Don't know what happened to them.

The initial JFETs that I tried in the LFO circuit mentioned above were just randomly selected. They were both in the middle of this profile but were not "matched." Using two JFETs with "matched" profiles and the largest available Vgs swing gave a wider controllable range of LFO frequencies.

Good to see my suspicions confirmed. I'd have guessed at that result. You don't have one going into one end of its triode region while the other is still in the middle.

One question I have about this data is whether or not it is really useful for the use I am considering because the triode region of a JFET is supposed to be in the region where Vds is below the pinch-off voltage, which I would think is less than 4.7V. Do I have this correct?

You do, pretty much. Actually, the good range of resistive operation is well below the actual saturation operation. The Geofex tester does not really attempt to do a triode region measurement, by the way. It's a matcher, not a measurer, with no pretensions to be otherwise. When I was doing that, I deliberately simplified it down to as bare-bones as I could, guessing that many people would still have trouble getting it to work; that turned out to be prescient, unfortunately.

What would be much better for your purposes would be to actually measure resistance, instead of Vgs to get a specific current. If you like, I'll see if I can find/concoct something to do that. 4.7Vdc on the drain is actually confounding your results some. They still come out working better matched, and let you see the funny ones, but the actual resistive behavior is a bit obscured.

[merlinb]

In case the point hasn't been made, any JFET can be used as a variable resistor. The two important things to remember are:

1: The signal voltage appearing across the FET (drain to source) must not exceed 1Vp-p, otherwise you exit the linear region and will get clipping.

2: The smaller the Vgs(cut-off) voltage the more 'fiddly' it will be to control, but this is not such a great handicap. In a 9V circuit you'll want to avoid FETs with a Vgs(cut-off) greater than about -3.5V, otherwise you may run out of headroom.

[Ronan]

Is there any advantage using a JFET versus a transistor say a 2N5088 as is used in the Bassballs?

[boogietone]

Is there any advantage using a JFET versus a transistor say a 2N5088 as is used in the Bassballs?

For use as a voltage controlled resistor (VCR), the FET is better. The physics of the two devices are different. It may be possible to arrange a circuit in which a bipolar transistor acts like a resistor, but I am not aware of one and it would likely have a very small usable domain and be difficult to control.

The action of a VCR is to set the voltage at one pin of the device and have the current through the other two pins be a function of the voltage across them in the same way that the current is a function of the voltage across a normal resistor, i.e. Ohm's law, V = IR or I = V/R. For a JFET, you set the voltage of the gate with respect to the source (Vgs), and as long as the voltage between the drain and the source remains below a certain value, the current between the drain and source is a function of that voltage between the drain and source, i.e. I = Vds/R', where the value of R' (R-prime) is dependent on the specific JFET. Also, the value of R' is a function of both 1) the voltage at the gate (Vgs) thus giving us a voltage controlled resistor AND 2) the voltage between the drain and source (Vds). It is this latter point that makes the "JFET resistor" non-linear. This region of operation for a FET is known as the triode region as opposed to the saturation region where the current from the drain to source is (almost) completely *independent* of the drain to source voltage.

Comparably for a bipolar, the circuit would be one of setting the base voltage with respect to the emitter and then having the current from the collector to the emitter be a function of the voltage between the collector and the emitter. The physics of a bipolar transistor do not work this way.

[R.G.]

In case the point hasn't been made, any JFET can be used as a variable resistor.

Yep. They all have that "triode region" that makes them work that way.

1: The signal voltage appearing across the FET (drain to source) must not exceed 1Vp-p, otherwise you exit the linear region and will get clipping.

Mostly, depending on the circuit conditions. JFETs have variable resistance all through the triode region, which extends up to Vp. If you run them at 0Vdc for lowest control voltage feedthrough, what actually limits the undistorted signal by diode clipping of the gate-channel diode in quadrant III. If you bias them up into the middle of the triode region, they can take more signal without clipping.

That gets touchy (in UK English: fiddly two countries divided by a common language ) to maintain, introduces another way the JFETs can vary, and also makes the control voltage feedthrough worse because now it's amplified by the JFET. But I've seen it done.

2: The smaller the Vgs(cut-off) voltage the more 'fiddly' it will be to control, but this is not such a great handicap. In a 9V circuit you'll want to avoid FETs with a Vgs(cut-off) greater than about -3.5V, otherwise you may run out of headroom.

Yep. I think I mentioned that the headroom you run out of is the control voltage. One way to work around this is to bias the source and drain up at 9V, giving you the entire 9V supply for reverse bias on the gate-channel. Like all good instant solutions, this introduces other issues, notably the fact that any noise on the 9V supply now feeds into the signal modulating JFET and the fact that you can't use the DC bias conditions in the circuit to hang the drain and source on. Sigh. TANSTAAFL (There Ain't No Such Thing As A Free Lunch    ).  As a practical matter, you get more improvement from doing the drain-gate feedback to lower the effective gate-channel signal voltage than messing with DC biases across the channel. I think this is one reason a lot of people like the Phase 45 sound.

For use as a voltage controlled resistor (VCR), the FET is better. The physics of the two devices are different. It may be possible to arrange a circuit in which a bipolar transistor acts like a resistor, but I am not aware of one and it would likely have a very small usable domain and be difficult to control.

Yes: JFET better in terms of size of non-distorted signal it can take and DC offsets, and the physics are very different.

There are some examples, notably the Seamoon Funk Machine, Dr Q, EH Pulsar, and probably Bass Balls. EH was big on using cheap devices for varying filter frequency. It works, but it's not great.

[merlinb]

If you run them at 0Vdc for lowest control voltage feedthrough, what actually limits the undistorted signal by diode clipping of the gate-channel diode in quadrant III. If you bias them up into the middle of the triode region, they can take more signal without clipping.

Not sure what you're getting at here. For most JFETs Vp is about 1V, but you run out of useful linear resistance long before that- closer to 500mV drain-source. Since the device is bidirectional you have 1Vp-p to play with altogether (no DC), unless you can tolerate the distortion, of course. Biasing them up will increase headroom in one direction, but choke it off in the other. Having zero DC across the FET is always the way to go if you want max headroom.

[PRR]

boogietone  --- I love the plots.

As R.G. says, his tester isn't working in triode mode. It is really an "amplifier" tester. To a quick approximation, "matched for amplifier" is good-enough for "matched resistance". When you poke to extremes, it isn't telling you the right thing.

For a better job, keep the voltage across S-D to <<Vp (below 0.1V, unless you know you have high-Vp parts). It may be simplest to apply a steady 10mV and measure current. Also you normally do NOT force Gate more than 0.5V above Source-- it conducts big and that upsets the signal you are resisting.

> It may be possible to arrange a circuit in which a bipolar transistor acts like a resistor.....

There is an old National datasheet LM389 showing a cassette recorder where the AGC is a BJT shorting the microphone. IIRC the early editions included AGC curves, and they were "acceptable" over such a wide range that any gross distortion mechanism was unlikely. The signal level IS very low, and so were expectations.

You can also attenuate by varying the current in a diode. Which could be a diode-connected BJT.

Both schemes are LIMITERS, in the sense that the signal across the BJT is controlled to be SMALL. In a phase-shift scheme the signal is not self-limited and may be "large".

> triode region, which extends up to Vp

Vp minus Vgs, isn't it? So as resistance rises (Vgs approaches Vp) the linear zone gets smaller (approaches zero). There's a trade-off here, desired signal swing and desired circuit impedances.

> "We use the #57 diffusion line..."

"Process" is the mask. Here's a few:



(There is no Process 57 in my book.)

While there is some difference in size, the main difference is the amount of zig-zag. The total length along the zigs is the "width" of the channel. A low-low current FET has a one-zig gate. A high-current (low ON resistance) FET is dozens of zigs, more total effective width.

Even among masks with similar zigginess there are some details of stray capacitance or intertwining.

OK, you lay the masks on wafers and then you run your diffusion recipes. "4" on the dopant knob and 10 minutes baking makes a low-Vp FET; "7" dopant and 15 minutes soak gives a high-Vp batch. Control is not very good. BJTs are mostly sensitive to Area; JFETs are area times diffusion depth, and maybe oxide thickness also (I'll re-re-read Oxner again).