Another way to match JFETs?

[armdnrdy]

As some of you may know, I've been working on the Roland Jet Phaser circuit and have worked extensively with different JFET types and different matchers.

One thing that kind of struck me was post where a Jet Phaser owner removed the factory 2SK30s from his phaser and tested them in R.G.s matcher.
They were nowhere near as "matched" as the JFETs I've been working with. In my opinion, I would not have used that set! I've closely matched a set with R.G.s matcher, and then culled the bunch by matching them with the ROG VP matcher, before matching the "on" resistance. I get "good" phasing but not as good as the sound samples I've heard from the Jet Phaser.

This leads me to believe that Roland used some other form of matching.

After studying a significant amount of material on JFET matching, I've been kicking around a few ideas to come up with a simple way to match JFETs to a particular circuit.

My take on what I've read so far is that the "perfect" scenario for JFETS acting as variable resistors in a phaser circuit would be for all JFETs to closely follow a similar track of drain-source resistance while being manipulated by a variable voltage at their gates.

My thought is to measure the min/max drain-source resistance with the actual phaser circuit's LFO/bias applied to the gate.

It seems that if we took measurements in this way we could find JFETs that "play nice" together in the realm of a particular LFO sweep.

I'm not too sure how to set up a JFET for a test such as this. If anyone has any ideas, please pipe in. I would like to experiment with another form of matching to see if it makes a difference.

[R.G.]

You could do it the obvious way. Set up a resistor and a JFET as an AC voltage divider. Set up a pot and a voltmeter on the Vgs. Apply an AC voltage to the divider side, and twiddle the pot until the AC voltage across the JFET is exactly the same as the voltage across the resistor. At this point, the JFET rds is the same as the resistance in series with it. Now, write down that gate-source voltage. Go to the next JFET.

... well, kinda. When you get JFETs matched this way, it's a one-point match, and tells you nothing about the vgs for other values of rds.

So we start again. Same setup, but with ten different values of series resistance to test against. Do the same test for each of the ten series resistances, noting the Vgs needed to match the series resistance for each one. Trust that the curve is not wildly different between any two values of rds and vgs. Graph the result.

Do this for each JFET. This results in a curve of rds versus vgs for each one. Now pick the best-matched curves. You have a ten-point (or as many as you can stand to do-point) match. It's mildly labor intensive, but it does the job of getting JFETs very much alike in the result of rds versus vgs. Note that this test does in fact test what you actually want the JFET to do in the circuit, that being an AC-signal resistor, and does (well, OK, *can*) test it at reasonable values of resistance and signal level. And the results can be measured, and probably automated.

One could even gen up a bridge-type setup to help sense "OK, the signals are matched now", as well as a uC to run the test and spit the points into another computer for graphing, automated matching, report printing, evaluation of different batches/manufacturers, etc.

There's probably some JFET theory somewhere that would say what the curves would look like, but I have this distrust of JFETs, and until I got the actual data, I'd be very suspicious that they were engaging in conspiracies in the box to be different. 

[armdnrdy]

Thanks R.G.

I know this whole JFET matching thing must be getting old for you!

I'll put together a circuit based on your description.

[Gurner]

I'd have thought a digipot under mcu (PIC) control would be the way to approach this (if you want to automate as much as possible & avoid a lot of manual plot charts!)

If you are going to try & match jfets so precisely (to get similar resistance traces), then are you going to go for equally tight tolerances for the filter components in the allpass?

[warning hypothesizing follows]

I've often wondered about how such attention to close tolerances/jfets affects the end results? (other than in the ear of the beholder)

You got a whole heap of frequencies being affected by differing amounts of phase delay by the allpass...differing frequencies are going to have different phase shifts going on, so even with matched components ...so you've already got a whole heap of different phase shifts at any one point for any given frequency (like a mind boggling amount)...I'm no phaser expert, but this seems to me a case of chasing a holy grail of matchedness, when in fact even with theoretically perfectly matched all pass filters, you've not got perfect phase relationship across all frequencies in the first place ....for example for a random 'snapshot' in time 82hz might be phase shifted 30 degrees, whereas 922hz might be phase shifted 276 degrees....which one are you shooting for? (A: all frequencies...and they all have different phase shifts) You've then got all the cancellation & augmenting going on depending on the frequency/phase shift.....which isn't going to necessarily be sonically enhanced by matching just one element (jfet) of the overall phase shift per stage.

My thoughts are so long as each individual stage is smooth (no 'steps'/jumps in resistance due to say the jfet straying to far out of it linear region...and causing a whacking jump in phase shift at the peak of an LFO swing), then the RDS matching won't necessarily improve the audible end result....but like I say, I'm no phaser expert, so I'll get me coat!

[R.G.]

I'd have thought a digipot under mcu (PIC) control would be the way to approach this (if you want to automate as much as possible)

Yep, that's how I'd do it if I were doing it. I'd make a bridge with two ... 10K should do, I guess, in series on the fixed side of the bridge, a 100K (?) digipot on the variable side in series with the JFET. Then I'd set up a way to make the uC put a variable voltage on the JFET Vgs, perhaps by floating the bridge center either on the + side of the power supply for N-channel and - side for P-channel so the uC could work within 0-5V for the Vgs output, presuming that JFETs over 5V Vgs are not all that useful on 9V pedals. Actually, I'd probably make the VGS be a digital pot too.

I'd use fairly good differential amplifer on the measurement nodes of the bridge, and feed the output of that to the uC A-D for sensing zeroing of the bridge.

The measurement would set either the series digital pot and adjust the Vgs pot to zero the bridge, or set the Vgs pot and adjust the series pot to zero the bridge, either way works.

Once a set of measurements are taken, the sensed pairs of Vgs/rds could easily be output by RS232, 1-wire, 2-wire, USB, etc, or stored in EEPROM for a dump later. Light the "done, next device..." LED.

Should take a couple of hours of circuit design and programming. Takes far longer to solder up the parts to do the hardware.

[armdnrdy]

but like I say, I'm no phaser expert, so I'll get me coat!

Neither am I!

I just know that when I see the word "selected" next to the JFET type in an old phaser schematic, and I try all of the available matchers with less than stellar results, my inquisitive mind and investigative nature leads me to find a better solution.

Whether I find it, I'm led in another direction, or I am just searching for the Holy Grail, that's to be seen.

Anything is worth a try......and sometimes two!  

[armdnrdy]

Okay,

While a PIC would be the way to go, the programming is a bit more than my head can take at this time!

I had a thought about R.G.s previous post. It seems as if we're comparing voltages in the voltage divider set up.

Can we use a multi level comparator circuit?

http://home.cogeco.ca/~rpaisley4/Comparators.html   (third circuit from the bottom)

Use the output of the JFET as the reference voltage, adjust the pot that's between the gate and source until it matches one of the predetermined resisted voltages. When the voltage match is achieved, a led lights up and with a DMM across the FETs VG, a measurement is recorded.

Would this work??? or am I batty? 

[R.G.]

I had a thought about R.G.s previous post. It seems as if we're comparing voltages in the voltage divider set up.

Can we use a multi level comparator circuit?

Yes.

But. (you knew that was coming, right?  )

We need to talk about error budgets. The idea of matching inherently contains the idea of "how closely do (or can!)I match them?"
Every measurement process contains some inherent error. The human eye, for instance, can generally only match physical alignment to no closer than 0.005". Looking at the alignment of two edges generally produces an error between +/- 0.005". Closer than that is luck, or you need magnification, as well as being no older than about 20 years.

A window comparator has some window size, where you get a "good" indication if it's between the bottom and top of the window. The problems related to this include (1) how precisely can you define the window, with resistor tolerance, bias and leakage currents, and the circuits that sense the window. Even if you can do this perfectly, you get to (2) window size: you can't measure finer than the size of the window. In general, you can't tell measurements just above the bottom of the window from ones at the top of the window, so the average error of a window comparator is 1/2 the window size, after the errors in defining the window are taken into account.

Making tiny little windows is a problem, because it may be impossible to set the measurements to get within the window. Go try to set your faucet to drip at 1.0 drips per second, as recorded over 1 minute. The problem becomes obvious.

It gets worse when you try to do multiple measurements and then window compare them. The thesis of this thread is multipoint matching ( 'cause I perverted it into that direction...  ) and you have to do multiple tests and window compares. Now you get 1/2 window size errors on each measurement, on average, and so the errors accumulate. The nice lines of rds versus vgs become bands.

In fact, the digital set-and-measure is a window comparator setup. Each pot setting has its error band, and the digipots will have error specs of 0.05 to 1.0 lsb per setting on how finely they can be set, and the A-D on the uC will have integral and differential nonlinearity of some fraction of an LSB on how finely they can resolve a measurement. Many windows.

So - yes, you can. But ensuring that what you get was worth the effort and not just fooling yourself about how closely you can read things gets sticky.

I am messing about a bit with the FET matcher I sketched out a couple of posts ago, just out of malevolent curiousity.

[armdnrdy]

Once again....Thanks for the explaination.

I'm looking forward to seeing what you come up with!

[armdnrdy]

I drew something up that I believe is the circuit as described by R.G. in his first post of this thread.

http://www.aronnelson.com/gallery/main.php/v/diyuser/Multi+Point+JFET+Matcher_001.jpg.html

Is this what you were thinking of R.G.?

[brett]

Hi
I'm not much of a theorist.. so my ideas are often a bit simple and weird.. but here goes anyway...

Often the best test-bed is the circuit itself. So let's imagine putting a socket where the jfet to be matched will go. When we turn the circuit on, what is the JFET doing? If I'm right, it's working as a variable resistor (yes?). If the resistance of the rest of the JFETs part of the circuit is constant, we can measure the variation in Jfet resistance by monitoring the voltage drop across it (yes?). You could do this with a scope or maybe by plugging it into the audio socket of a laptop and using some sort of scope/datalogger/??? software. You might even get by with using the AC voltage setting on a DMM (probably asking too much, given the ).

Look for the same curve of voltage drop across the S-D of the JFET. The ultimate match would be the same (absolute) voltages. With any luck, the main differences between devices will be in the max and min resistance, and the curves will be similar shapes. But as RG says - you just can't trust JFETs - getting to work together is harder than herding cats.
cheers

[gritz]

I like brett's cat herding analogy...

Looking at the Jet schematic (for the first time) I see that the fets are in parallel with 100k resistors. This sets the fet's upper level of it's area of influence with regard to interacting with the 10n capacitor, so testing the fets for their Vgs for 100k resistance might be a good place to start (and 10n @ 100k + 100k equates to about 320Hz iirc). But R.G. mentions that this only gives us one point in the area of operation, so let's look at the other end of the gitahh frequency spectrum - say 6kHz. For our 10n cap that equates to 5.3 kilo-ohms resistance (I think). So I'd test a few fets to measure what Vgs equates to that resistance (I'm ignoring the minimal influence that the 100k in parallel with the fet would have).

Let's say that our very rough measurements of a handful of fets give us these average figures:

For 100k series resistance Vgs = -2.54V
For 5.3k series resistance Vgs =-1.78V (I'm making these up btw!)

So we grab our resistance meter, a bit of vero, a switch, some trimmers, etc and make up a little board that can apply -2.54V, -1.78V and maybe a figure somewhere in between to the gates our pile of fets. This way we can see the variance in a reasonably real world situation, rather than just making arbitrary measurements and worrying whether they're at all relevant.

"That's all fine and dandy, but how closely do they need to be matched, dammit?!!!"

That's the million dollar question! A variance in resistance of 100% between fets (i.e. the difference in resistance between 5.3K and 10,6k) would give a filter error of one octave between allpass sections, which might be a bit much - but then again chasing the last ten percent may be an effort in pointlessness too. I'd be tempted to breadboard the allpass array, but using fixed resistors insted of fets. I'd squirt a signal in there and change out a few of those resistors to see what effect those "errors" have on the sound and then I'd go from there.

But then I do have a lot of time on my hands...

I hope that this stream of conscienceness helps a little.  

Edit: It does occur to me now that fractional allpass phase leading whatnot is a bit more complicated than the simple 1/(2*pi*R*C) thing, but I think I'm on the right track. Possibly.

[R.G.]

Brett, you're right that in general, the circuit it's being used in is the best test bed for actual operation of a component. And the technique you suggest would work.

There are some practical problems with the approach which are more from the sorting/selecting side. The first problem is instrumentation. Using the JFET in a typical phaser circuit involves floating it at some bias voltage off ground. Not a big problem, but it makes it tricky to monitor voltage because you need to either have a floating O-scope, meter, or differential probe. Not a huge problem, but the details will matter. Floating measurements are a problem for beginners in general. If I were doing this, I'd make a similar-but-modified phaser stage to test in. Details to follow.

You do definitely want to use an AC signal for testing the rds, because the DC levels will be floating. And you want to use a really BFC for coupling so that you don't have the phasing cap causing signal level changes with changing signal frequency. Mucks up your measurements. So the circuit needs a bit of mod.

The second set of issues are operations-research kinds of issues. If the objective is to match one JFET to three or more already matched, it's easy. Just substitute trial JFETs until you get one that matches by whatever test method you use. If none are perfect, pick the closest one. This is an order-of-N problem, where N is the number of possible single JFET matches. Picking the best-matched four (or more) JFETs out of a batch of N is a bigger problem, because you effectively have to compare all combinations of four JFETs out of the N to be tested. Having picked one JFET, you have to test N-1 against it. You then have to test N-2 against the pair, and N-3 against the trio. So you have to do an order-of-N-cubed number of tests. And that leaves out the big problem of how you pick the first JFET as the standard. What you don't want to do is to have to do N tests of order-of-N-cubed tests to find the first one. This gets out of hand rapidly as N goes up.

The way to get around that is to measure all N in some kind of number for each one, write that down, then do the matching for all the numbers to pick the best matched several. That cuts the tests down to N instead of N³ or N⁴ plus some math and perusal of numbers. Again, this works if you have a datalogger reading from the in-circuit-test and storing the numbers.

Approaching the test from this direction, I'd make a modified phase stage that didn't phase. I'd make up an opamp stage with the (+) input being fed a signal voltage through a big capacitor, through a resistor, and into the + terminal, and the JFET shunting the + terminal to a bias voltage. I think the (-) input side could be just connected to the output through a resistor for gain-of-one. Feed in a signal, watch the signal at the output of the opamp. When the output signal is half the input signal, the JFET rds is equal to the series resistor at the input, neglecting the capacitor impedance. Actually, providing the input signal from the output of another opamp would ride through the bias voltage and side step the capacitor entirely for this stage anyway.

There are two ways to go. You could use a fixed series resistor and assume that the output voltage is proportional to the JFET resistance according to rds/(R+rds), which gives you a varying signal voltage to measure, or change the series resistance to keep the output signal voltage up. I'd probably use a varying series resistor to avoid the measurement issue on the output voltage level.

In either case, you have to then measure the output signal level. This can be done by a scope-equivalent. I have been mentally tinkering with cheating on this. I'd make the AC signal be a square wave of about a volt peak, then put a switch-hitter on the output to invert every other half-cycle and convert the square wave to a DC level, and measure that. I liked that because I could measure the recovered DC level with the A-D on a uC simply and have my single number for the rds at the test level of Vgs. Once I'm there, I'm out of the the analog domain and into numbers in a computer.

You have the choice of either varying Vgs to get to a certain rds, using fixed Vgs steps and measuring the resulting rds. Both methods produce a valid set of points on the hypothetical vgs/rds curve you're measuring.

[R.G.]

N.B. I simulated the analog path with a series resistor, square wave AC in and switch hitter to make DC out of the output signal. That seems to work OK.

I'll have to mess with it some more about the value of the series resistor and whether to make Vgs or rds the independent variable.

[armdnrdy]

R.G.

I'm glad that this thread has rekindled your interest and passion for "building a better mouse trap."


I'm anxiously awaiting your results!

[ashcat_lt]

You got a whole heap of frequencies being affected by differing amounts of phase delay by the allpass...differing frequencies are going to have different phase shifts going on, so even with matched components ...

It is precisely the frequency dependent phase shift which makes a phase shifter do what it does.  If all frequencies are shifted by the same amount, then - when you mix it back with the original - you get a broadband attenuation or reinforcement.  Run the LFO and you get broadband amplitude modulation = tremolo.  There are much easier ways to accomplish that!

I do, though, also wonder what the effect of a mismatch can be.  If one stage delays a given frequency by, say, 90 degrees, and the next shifts that same frequency by 100, you wont get full attenuation at that particular frequency, but doesn't there almost have to be some frequency where the two filters add to 180?  Things are a little fuzzy here today, so maybe my thinking is a bit off.  

[gritz]

You got a whole heap of frequencies being affected by differing amounts of phase delay by the allpass...differing frequencies are going to have different phase shifts going on, so even with matched components ...

It is precisely the frequency dependent phase shift which makes a phase shifter do what it does.  If all frequencies are shifted by the same amount, then - when you mix it back with the original - you get a broadband attenuation or reinforcement.  Run the LFO and you get broadband amplitude modulation = tremolo.  There are much easier ways to accomplish that!

I do, though, also wonder what the effect of a mismatch can be.  If one stage delays a given frequency by, say, 90 degrees, and the next shifts that same frequency by 100, you wont get full attenuation at that particular frequency, but doesn't there almost have to be some frequency where the two filters add to 180?  Things are a little fuzzy here today, so maybe my thinking is a bit off.

So build the allpass sections with resistors instead of fets + lfo and swap out some values and see what happens! (I think I mentioned this before...) We could spend until next Christmas talking about how to measure fet parameters, but unless we understand the effects that those tolerances have on the circuit it's a complete waste of time.

Build the guts of the phaser, (or replicate it in software) and feed some variables in there. No point worrying about the fet values 'til you know what is going to break the circuit imo. It's even possible that the 100k / 10n paradigm is sub optimal for the bag o' fets that you have, so be prepared to start again. Very often the reason that an analogue whatever sounds good is because someone made a mistake, or assumed something without adequate knowledge, or stole an inappropriate application from an old RCA catalogue...

I'd suggest (again) working out why the original circuit does what it does, rather than micro-analysing the individual components and missing the holistic whatnot. 

[R.G.]

I do, though, also wonder what the effect of a mismatch can be.  If one stage delays a given frequency by, say, 90 degrees, and the next shifts that same frequency by 100, you wont get full attenuation at that particular frequency, but doesn't there almost have to be some frequency where the two filters add to 180?  Things are a little fuzzy here today, so maybe my thinking is a bit off.  

See "The Technology of Phasers and Flangers" from 1999 at geofex: http://geofex.com/Article_Folders/phasers/phase.html

[armdnrdy]

I think that you guys should go back and read the part about "selected" in my third post. As I stated in my first post, I have matched JFETs everyway upside down! But still I'm not getting quite the sound out of this phaser. Now I can call it good and move on to the next thing, but that is not my nature.

Manufacturers of phasers don't just throw any JFET in and call it good. I think we all understand that. What I'm trying to do is find other ways of matching the JFETs to see if it does in fact make a difference from the ways that we commonly match them.

I understand that you can have JFETs that are matched to each other but "out of range" for the pass components but.....I have never seen written in any old schematic "selected" or "matched" by any of the pass components.

To me it makes perfect sense to match several points of vgs verses resistance.

[gritz]

I think that you guys should go back and read the part about "selected" in my first post. I have matched JFETs everyway upside down! But still I'm not getting quite the sound out of this phaser. Now I can call it good and move on to the next thing, but that is not my nature.

Manufacturers of phasers don't just throw any JFET in and call it good. I think we all understand that. What I'm trying to do is find other ways of matching the JFETs to see if it does in fact make a difference from the ways that we commonly match them.

I understand that you can have JFETs that are matched to each other but "out of range" for the pass components but.....I have never seen written in any old schematic "selected" or "matched" by any of the pass components.

To me it makes perfect sense to match several points of vgs verses resistance.

Am hearing you - and have heard you from your original post.

Let's look at the situation. We have no evidence from the oem regarding the desired parameters of these "matched" fets whatsoever. Without at least a bit of anecdotal evidence re. whether they tested and binned onsite for ~whatever~ params, or whether thay bought in a lorryload of specced fets, or whether they didn't care much at all then it's all meaningless - you've hinted as much yourself. Sorry to sound harsh - but without any concrete numbers you're going to have to reverse engineer the circuit by thinking in the same way as the original developers did - and I don't expect that they had the analytical luxuries that we do, nor the time, or much budget. They doubtless had some wisdom (received or otherwise), so it's up to you to figure that out.

Try and find out who designed the circuit (or who he / she stole it from). Have a look at other products that the company was building at the time. Put yourself in the designer's shoes. Look at the other components in the product. Are the allpass caps "specced", or are they cheapo items with a wide tolerance? At every point ask yourself "why did they do it like this?"

Treat it like forensic research. And don't forget that most commercial products are built to a price, so it's easy to over-think everything.