Common Source JFET stage question

[jh9067]

Hi!

Hoping someone out there has the patience to illuminate something for me...

In designing a common source JFET circuit, I've read a few times that Rs more or less sets the gain in addition to it's biasing function. 

Three questions:

1. Is this correct
2. If so, is it acceptable to use a pot here for gain control?  This appeals to me because it seems to remove the pot from the signal path. So lastly,
3. Is that assumption correct?

Thanks!

JH

[kingswayguitar]

I can only help a bit until someone wiser adds to the discussion.
Assume an N-channel JFET.
BIAS
Rs can set all or some of the bias.  Some common designs also use a voltage divider at the gate to influence the bias, but Rs is very important in both cases.  You`re on the right track.
GAIN
The gate to source voltage (bias) sets the idle current, which defines the transconductance (current gain per input signal voltage).  The size of the drain resistor then sets the output voltage gain (bigger resistor, less voltage - Ohm;s law).  If there is a capacitor connected from source to ground (source bypass capacitor), then gain will be maximized, but the size of the capacitor is related to the frequency where gain is most pronounced (bigger capacitor extends the gain down to lower frequencies).  Putting a resistor or pot in series with the capacitor will reduce the gain.  So there`s your single gain control.

Curiosity...does the common source JFET define your entire circuit or are there additional stages involved

[R.G.]

In designing a common source JFET circuit, I've read a few times that Rs more or less sets the gain in addition to it's biasing function. 
Three questions:
1. Is this correct

Somewhat.

A JFET is most simply modeled as a transconductance. A voltage change on the gate-to-source causes a resulting change of current flowing from drain-to-source. It's more complicated in reality but this is a good place to start. So the gain winds up being the transconductance (change-in-channel-current per change-in-gate/source-voltage) times the drain resistor.

When you add a source resistor, the voltage on the source rises when the current in the channel rises. It's in the direction to reduce the input voltage change that created it, so it's negative feedback. It cuts the gain down from the value it would have had.

Looked at another way, there is no current going into or out of the gate, so the same current going through the drain goes through the source, and the gain becomes Rd/Rs. I believe this may be the origin of the "Rs sets the gain" thing. If the raw transconductance were very high, the gain equations would reduce to Rd/Rs. But JFETs don't have a lot of transconductance, so the actual gain you get is less than Rd/Rs.

So, yeah, Rs "sets the gain", but it does so in conjunction with the transconductance (which varies!) and drain resistance.

2. If so, is it acceptable to use a pot here for gain control?  This appeals to me because it seems to remove the pot from the signal path. So lastly,
3. Is that assumption correct?

It's OK, but the degree to which it's OK depends very much on how big the signals are you're amplifying. Changing the source resistor does major changes to the DC bias point, and that causes major changes in how big a signal you can amplify before getting distorted. You might like the distortion, but it's confounded with the gain change, so you can't change them separately with a simple pot on the source.

What you can do is put a fixed resistor on the source to set the DC bias condition, then use a BFC from the source to a pot to ground, and let the pot to ground set the impedance for AC conditions at the source. This is done all the time for fixed conditions to get stable bias with a fixed source (or emitter!) resistor, and some of the lost gain recovered with a series cap/resistor. The resistor can be made a pot. Range is limited, and you may need big BFCs.

[PRR]

> it seems to remove the pot from the signal path

Not at all.

There's TWO signal loops.

* Gate to Source

* Drain to Source

BOTH pass through your Source pot.

But what is wrong with a pot in the signal path? Everything you've ever heard electronically has been through multiple signal pots.

What's "wrong" with your plan is that this is also Source _bias_ control.

Changing this resistance DC-wise throws your FET way out of a happy-zone.

Leaving the DC bias resistor and shunting it with a cap-coupled variable resistor will increase gain, but not decrease it. Good for some situations. However smooth control needs a reverse-taper pot.

Cap can generally be 22uFd. Few FETs at audio-rational currents have Gm below 2,000uMho, which is equivalent to 500 ohms, and one 22uFd+500r pole will pass lots of bass.

OTOH: why ask? You can breadboard this in a jiffy. Watch that all your DC voltages stay "reasonable". In particular, Drain should normally be well inside the supply lines, not stuck at +8.9V or slammed way close to Source voltage.