I have yet another weird problem I haven't encountered before (FET related)

[Paul Marossy]

OK, so I have yet another really weird problem I haven't encountered before....

I'm currently working on a FET simulation of a tube circuit (which I can't share here) and I got it sounding pretty good except for I have one problem that recently developed: after playing for 3-4 minutes it's like the power goes away and then it sounds really misbiased.

I've traced the problem to Q1 (a J201), somehow the FET drain is getting more than half the supply voltage, like I don't even have a trimpot installed between 9V and the drain set for half the supply voltage. Q2 thru Q4 are steady and don't have this problem. If I let it sit for 10 minutes it goes back to normal and then the process repeats itself. So I surmise that I'm probably having a problem with ultrasonic oscillation somewhere around Q1. I don't suspect the trimpot is faulty because it seems to be functioning perfectly normal. I have a 100uF filter cap on the power supply.

On the actual tube circuit, there are some small caps (.001uF and 470pF) in parallel with the B+ resistors on the plates of the preamp tubes. Would this be to prevent oscillation? I don't have these caps on my drain resistors and I'm wondering if adding one would solve this strange problem. Any second opinions to throw out there until I'm done with voluntary slavery today and can go home to work on it?

[R.G.]

That sounds much more like a thermal problem than oscillation. It may be that a thermal problem lets it start oscillation, but I think it's actually thermal to start with.

Ultrasonic oscillations would not need a cool down period. They stop when the power goes off.

There is one subtle feature of JFETs that doesn't get much play. The gate of a JFET gets very, very leaky when it gets hot. At high temps, the gate input resistance may drop from near-infinite down to well under 1M, which leads to some odd behavior if you counted on it being very high.

Time for an oscilloscope.

[Paul Marossy]

A thermal problem huh? Never thought of that one. Very odd to me for it to be happening in a 9V circuit.

[Earthscum]

I can't remember the circuit I was playing with at all, but I had an issue where a cap was getting pumped by my guitar (bass) signal. The more I played, the higher the voltage would raise and start to mis-bias. After I'd stop for a moment, the voltage would settle back to where I had originally set it. I kind of remember putting a resistor in series with the input and it stopped it. I believe my thinking was that (probably a fet circuit, thinking about it) if I reduce current, the voltage would have more time to bleed down than get pumped up. Maybe give that a try?

[Paul Marossy]

I can't remember the circuit I was playing with at all, but I had an issue where a cap was getting pumped by my guitar (bass) signal. The more I played, the higher the voltage would raise and start to mis-bias. After I'd stop for a moment, the voltage would settle back to where I had originally set it. I kind of remember putting a resistor in series with the input and it stopped it. I believe my thinking was that (probably a fet circuit, thinking about it) if I reduce current, the voltage would have more time to bleed down than get pumped up. Maybe give that a try?

Interesting, kind of sounds like what happens to me. But I already have a cap and a resistor in series with the input.

[Earthscum]

breadboard, perhaps? Or where you built it on the board? I've had all sorts of goofy crap happen before I decided to get a new one (and sometimes just by where I built it, but that has always seemed to do more with clocks and such).

[Paul Marossy]

It's actually built on a PCB layout I made. It was working fine for a long time and then suddenly it's doing this business.  

[kurtlives]

Do you have a resistor from the gate to ground, a gate leak if you will.

[Paul Marossy]

Do you have a resistor from the gate to ground, a gate leak if you will.

No. Only have a 68K/0.01uF in series with input to gate of Q1 and a 1M pulldown resistor before those two items.

EDIT: The other three stages do, however. Hmm... maybe that has something to do with it. I'll give that a try when I get home from voluntary slavery.

[Earthscum]

How's your gate even biased?? It's just floating?

[Paul Marossy]

How's your gate even biased?? It's just floating?

Apparently it is. That must be the problem I guess. I'm much more familiar with opamps, so it's probably my own dumb mistake here. 

[kurtlives]

How's your gate even biased?? It's just floating?

Apparently it is. That must be the problem I guess. I'm much more familiar with opamps, so it's probably my own dumb mistake here. 

That's your issue for sure then.

Put a 1M resistor right from the gate to ground.

[Paul Marossy]

How's your gate even biased?? It's just floating?

Apparently it is. That must be the problem I guess. I'm much more familiar with opamps, so it's probably my own dumb mistake here. 

That's your issue for sure then.

Put a 1M resistor right from the gate to ground.

That's exactly what I was going to do. Live and learn!

[Lurco]

http://www.diystompboxes.com/smfforum/index.php?topic=59303.0

[Paul Marossy]

The 1M resistor seems to have taken care of the problem. Thanks for the help everyone in helping me to get educated 

[R.G.]

Well, there you go!

Sorry for the misdiagnosis. You're actually seeing the time for the nanomperes of leakage on the JFET gate to charge up your input cap.

[Paul Marossy]

Well, there you go!

Sorry for the misdiagnosis. You're actually seeing the time for the nanomperes of leakage on the JFET gate to charge up your input cap.

No problem R.G. It was just really weird, learned something in the process though. 

[Perrow]

I know it was a typo, but I do like the word "nanomperes"

[R.G.]

... uh... yeah! "Nanompers" are teeny, tiny, electrical baby clothes.

That's my story and I'm sticking to it.   

[duck_arse]

I have a question, perhaps inversly related to the solution here.

I know I can't control what is connected to the input of a pedal I build, so I put a blocking cap on the input stage. It seems common sense, even when it's a self biased fet input stage, maybe like a fetzer, for example. only not like a fetzer, they don't have input blocking caps on the rog diagrams, do they? and lots of other self biased fet circuits are also missing them.

am I missing something, or is bad practice accepted practice?

nanompers sounds like an eating something .