no trim 18VDC jfet circuit

[tca]

Glad you took a different, and better, path.

Cheers

[Gus]

This circuit is not something I came up with.
You can find it in one of the Vishay jfet app notes. 
It is also in books
It is the same type circuit I posted in another thread that used  + and - supplies this one is for one supply voltage
It is also for the j201 because it seems to be popular at this forum
for a different jfet that has a different range of IDSS etc you will need to change the resistor values
For a jfet like a 2n3819 this type circuit might not work well because off the wide range of IDSS, Vgsoff etc.
The gain is set low to limit clipping
It should have a cap at the fixed bias voltage node as pointed out by gritz and a lower value gate to fixed bias node resistor 2.2meg to 4.7meg might be good to start with.

This circuit has limitations and I think jfets should be measured and selected for use in different parts of circuits.

[pinkjimiphoton]

Ousb? Thread link? If pjp endorsed it like that, I gotta check it out;)

the best octave up...tracks the whole neck. almost unusable amounts of distortion.... crazy harmonics, sustain that jumps octaves as it blooms...

it's @#$%ing awersome. BUT... make sure you ground the cases of the pots together or it may oscillate!! a LOT of gain!!

if ya turn the gain control way down, you can get an almost "cleanish" octave up, too.

as with all of gus's circuits, major bang for the buck... low parts count, well and cleanly designed, and outstanding in use.

i mounted my sick box with a fuzzface in the same box. amazing combination of over the top.

sorry to hijack the thread again!!

[pinkjimiphoton]

ousb demo

[PRR]

> lower resistor in that voltage divider to be the same value as the source resistor?

No. Youse guys aren't looking or thinking. No wonder Gus gets so little response to his posts.

Let's simplify:



Gus biased the JFET Gate to 8 Volts.

How he got there (82K, 2,000Meg) does NOT matter.

Why?

Because if we know the JFET Source voltage, and Source resistor, we know the JFET current.

But with a random-pick JFET, with Gate at zero Volts, the Source voltage can be zero Volts or 4 Volts.

But-But: with the Gate held up at +8V, we *know* the Source voltage will be 8 Volts to 12 Volts.

Which is not much of a variation.

The 8V pre-bias overwhelms the 4V uncertainty in Vgs.

Now with a 10K Source resistor, we *know* the current must be 0.8mA to 1.2mA. And for initial design, we can use "1mA" as a starting point.

We have stabilized the JFET current. We won't have a way-out result.

The 8V battery does not supply "any" current. And is awkward. It can be replaced with a Voltage Divider.

Going further:

We want a Drain resistor to take the output. The value has no (1%) effect on current, unless it is so large the Drain is pushed into the Source.

Source is at 8V to 12V. We should allow a couple Volts across the JFET. So the lowest Drain voltage should be 14V. Highest is 18V. Audio swings both ways. We want to split the difference. 16V. That's 2V down from 18V. We want a resistor that drops 2V at 1mA. 2K is our Drain resistor.

Just like that, we have a stable circuit. But is it an amplifier?? It has no current gain because we have a solid 8V battery tied to the Gate. But the Gate draws no current. It will bias the same if we stick a 100K, 1Meg, even 2000Meg resistor between the 8V and the Gate. Now we can put some signal into the Gate, and very-small current, while we have good current in the output. So good current gain. How about voltage gain? Just like this, the voltage gain is less than 2K/10K or 0.2, or a loss. However we can change the AC/audio voltage gain without upsetting the DC bias with a Source resistor bypass cap. Now the voltage gain depends on JFET Gm, so you need to interpret data, or just Try It.

The 2K output impedance is rather small, and gain improves with lower current (higher Drain resistor). Gus' choice of ~~40K will increase voltage gain significantly, while still giving a low-enough output impedance for general audio circuits.

[mistahead]

That-thing-me-sideways...

I've been trying to understand these JFET tricks from Gus for a couple of weeks now and PRR - your rage offers clarity.

Props to both Gus and PRR - thanks!

[gritz]

As I threatened earlier in the thread I headed of to the breadboard, where I had an overclocked ICL7660SCPA spitting out +18V and =9V which I figured would allow me to use (almost) the whole of the +18V for signal and not worry about creating faux grounds that might induce noise and increase component count.

So, the concept:



Pretty simple really. We want the jfet drain to sit at V+/2, so Rdrain needs to drop 9V. As no current flows through the jfet gate in normal operation then we simply need to drop 9V across Rsource to achieve this - because an identical voltage will be dropped across Rdrain. Cbypass and Rgain are there to give us some AC gain and tonal shaping options. Within the bounds of the jfet's gm characteristic (and given a big enough Cbypass) the signal gain of the circuit will be Rdrain/Rgain. Very basically. As a ballpark, I've chained three fet stages and I'm using Cbypass of 470n  to rolloff bass and de-muddify and 470 ohm Rgain to flatten the passband, but more on this later...

However, two wrinkles conspire against us:

1) Due to normal fet operation the source will naturally sit slightly positive of 0V. This means that a bit more than 9V is dropped across Rsource and as an identical voltage is dropped across Rdrain our quiescent drain voltage will be a bit low. For our old favourite J201 fet it's not a lot, but it's there.

2) Our charge pump voltage doubler doesn't actually double the input voltage. The output voltage will actually be lower than Vin*2 to the tune of two diode drops. We can maximise efficiency by using Schottky diodes, but it will still be fractionally low.

Considering 1) and 2) above the obvious thing to do is to reduce our -9V a bit (technical term).

The hack:



This is the power supply I'm using. Schottky diodes D1 and D2 provide maximum positive oomph, while D3 and D4 reduce the negative rail voltage "a bit". D5 provides protection in the event that the load tries to pull the negative rail north of 0v.

The test circuit:



This shows teh numbers with some J201s that I have. Variations in the fets' VGS characteristic will be reflected by slight variations in the voltage in the source, but with the few that I had laying about the variation was a few tenths of a volt - not bad at all. Because of the high value of Rdrain the fet's drain can swing down to almost the same voltage as the source, so it's pretty close to the midpoint of the available voltage swing. If you're using fets with a higher VGS characteristic then you may need to reduce the negative rail voltage a bit further. However, with similar fets it's very repeatable and the 18V supply means that the odd volt here and there isn't a big deal at all.. If you want to set a different quiescent Vdrain (e.g. 2/3 Vsupply) then it's a simple matter of changing the source resistor to suit.

As I mentioned earlier I chained three gain stages together in a very vaguely Engl kinda way. The noise performance is good and it's making musical noises, but as with any high gain circuit sensible power rail decoupling is necessary to prevent noise and instability (self oscillation). My current layout looks a bit like this:



Even with the very low value dropper resistors in the supply rails the noise performance and stability seem good so far - but it may require tweaking if it ever gets to the pcb stage. I also have some low value (470pf) caps between the fet drains and ground - because there's no point reproducing the stuff that you don't want.

And not a trimmer in sight.

Hats off to Gus for prompting this bit of research.

[slacker]

Nice work.

[tca]

@gritz
> As I mentioned earlier I chained three gain stages together in a very vaguely Engl kinda way.

How much distortion/OD can you get out of it? Any sound clips?

I've been playing also with gain stages but wit BJT's (3 stages also), I've found that a big cap 1000u in parallel with the power source is enough for killing any oscillations.

Cheers.

[gritz]

@gritz
> As I mentioned earlier I chained three gain stages together in a very vaguely Engl kinda way.

How much distortion/OD can you get out of it? Any sound clips?

I've been playing also with gain stages but wit BJT's (3 stages also), I've found that a big cap 1000u in parallel with the power source is enough for killing any oscillations.

Cheers.

Hi tca - sorry I haven't gotten back to you earlier, this is the first time I've checked this thread today.

There's a lot of gain available - more than overdrive, really. It's pretty metal when flat out. Give me a day and I'll post a (very work in progress) schematic and I guess I'll have to open another Soundcloud account for those experimental clips and whatnot.

[Gus]

Looks good

I would have kept the more negative voltage and adjusted the Rsource resistor up a little in value.  The greater the voltage the more like a constant current device.

[gritz]

Looks good

I would have kept the more negative voltage and adjusted the Rsource resistor up a little in value.  The greater the voltage the more like a constant current device.

Yeah, that would work too - I was just keeping the resistor inventory down and reducing the need for actual maths! 

Substituting different J201s shows that it's pretty robust in it's handling of varying Vgs. My biggest initial worry was noise, but it's proved to be sweet - despite the fact that it's a total rat's nest on my breadboard.

[Gus]

gritz

I put your circuit into Lt spice to check the sim voltages against a real build I used +18VDC and -9VDC