voltage doubler cmos style

[kingswayguitar]

i dont use this stuff but i read others using charge pumps and voltage doublers. maybe this article is of use?

http://www.gyraf.dk/schematics/Voltage_multipliers_with_CMOS_gates.pdf

[Mark Hammer]

PAiA has been using this for a number of years now, for their various "starved plate" tube projects, like this one: http://www.paia.com/prodimages/siabsch.pdf

But thanks for the link to the article.  Man, I sure do miss ETI. 

[kingswayguitar]

PAiA has been using this for a number of years now, for their various "starved plate" tube projects, like this one: http://www.paia.com/prodimages/siabsch.pdf

But thanks for the link to the article.  Man, I sure do miss ETI. 

i was sure some of you veterans must have seen something like that before


but out of curiosity, in your link, i see the cmos/diode/capacitor voltage ladder. do you need a +ve voltage supply in front of the diodes to get the thing started? or are all those "cmos"s in your link just self oscillating? again, just a complete ignoramus here but looking to learn.

cheers

[Mark Hammer]

I probably should have mentioned (and PAiA should have drawn) a +15Vdc power connection to that 4049.  Only 3 of the invertors shown produce the "charge pump" effect, and the 3 remaining invertors are paralleled to provide greater current drive.  The network of caps and diodes serve to "collect" the pulses produced by that clock, summing them up to form a higher voltage, with a bit of ripple at - hopefully - ultrasonic frequencies.

[PRR]

> PAiA should have drawn) a +15Vdc power connection to that 4049

That was back in days when we could read. Lower right:

+15V pin 1 IC3
Gnd  pin 8 IC3

> are all those "cmos"s in your link just self oscillating?

*Given power* (see above), note three units chasing each other in a loop.

Whatever happens, happens over and over again. If there's any gain in the loop at positive phase, it gets bigger, toward infinity, subject to the 15V supply limit. So we have a nearly 15V p-p square-wave out of the CMOS.

3 naked CMOS inverters will self-oscillate around 15MHz. That's too fast for cheap diodes, so a cap and resistors slugs it down to maybe 23KHz. Above audio but slow enuff for diodes.

I *think* the PAiA plan is a "tripler". Ideally 45V. But the drawing says 30V. That's because a CMOS inverter (even a 3-team) has a lot of sag on load. In practice you do NOT expect a lot of current, and adjust the diode-cap string on test.

[knutolai]

Nice article. Is there a reason why we don't normally see any of these circuits in effect pedal schematics? Seems to me its a much cheaper way to add headroom than using a MAX1044 (or equivalent) voltage doubler.