Biasing a Mosfet question! Help required please =)

[Dylfish]

Hey Guys,
I'm still having issues with the biasing side of things when it comes to Mosfets. Can anyone please correct/confirm my thinking below? I have used a large theoretical input voltage since I eventually want to try a multi stage FET setup. Anything silly sounding or plain stupid just let me know 

VT = 2.0
Assumed Max Input = 3v p2p
Bias for 1ma

BS170 running at 1ma has an approx Transconductance on 10-15ms, I will assume 15ms (15ma/Volt).

Therefore to get the MOSFET biased at 1ma we have to:
= desired current / transconductance per volt
=1ma/15ma
=0.06v needed over the threshold to bias the circuit at 1ma.

VG
= VT + ½ Assumed Max Input + Bias Voltage
= 2.0+1.5+0.06
= 3.56v

VS
= ½ Assumed Max Input
= 1.5v

Therefore VGS = 2.06v, Just enough to keep the channel conducting enough to keep the circuit / FET at 1ma (approx).

If (and yes I'm aware that it's a large signal I'm putting into it) the guitar signal is swinging from +1.5 to  -1.5, wont the voltage on VS adjust with the change on VG, keeping the VGS the same? (eg VG drops 0.5v, so will VS). If this is the case how does
VS change in the first place since the current shouldn't be moving if VGS stays the same?

Is it a case of it moving so quickly that the changes back and forth on VS look like they are instant when they are not?

Also, if the current is changing along with the VG/VGS Voltage, if there is such a large (say half swing 1.5v) why doesn't the VGS which is only sitting 0.06v about the threshold go into cutoff?

Sorry if these questions may be stupid.
Cheers,

Dylan

[seedlings]

This may or may not help you, but here is the circuit with just about 1mA through Rs.



CHAD

[Dylfish]

Thanks Chad,

Im still not 100% following though. Im trying to nail this before I go onto anything else so Im hoping someone could explain how far off I am or not =)

[seedlings]

Thanks Chad,

Im still not 100% following though. Im trying to nail this before I go onto anything else so Im hoping someone could explain how far off I am or not =)

I thought it might help to see the voltages of a circuit set up at 1mA.  Problem is I'm not a huge help for equations... but, if you would like some values plugged into a simulator... that I can do.

CHAD

[Dylfish]

Thanks mate,

Ive got LTspice here too but im struggling with the theory side of it.

Cheers =)

[bool]

With spice, use the ".op" analysis (operation point). With it, you can probe around your circuit and the "math" behind it will "hit you" in the head once you get the grasp of it. Just sayin'..

But when you're at it, the most important to me seems the relation between Vgs and Is (source) when using a biasing network like the one that seedlings posted.

Vgs = Vg (junction R2-R3) - Is*R4

Is is projected onto Id (for all practical means equal ...), so Id = Is. This is imo the most important thing to know when dealing with mosfets, because the Vgs is so device-dependant.


googling "mosfet transconductance gain stage calculation example" returns alot of stuff to tinker with


My suggestion is to create a simple nmos gainstage project in LTS, use the ".op" analysis, get a vibe for it, and then decode the math behind it instead of going against the math first.

[R.G.]

I'm still having issues with the biasing side of things when it comes to Mosfets. Can anyone please correct/confirm my thinking below? I have used a large theoretical input voltage since I eventually want to try a multi stage FET setup. Anything silly sounding or plain stupid just let me know
VT = 2.0
Assumed Max Input = 3v p2p
Bias for 1ma
BS170 running at 1ma has an approx Transconductance on 10-15ms, I will assume 15ms (15ma/Volt).
Therefore to get the MOSFET biased at 1ma we have to:
= desired current / transconductance per volt
=1ma/15ma
=0.06v needed over the threshold to bias the circuit at 1ma.

OK so far.

VG = VT + ½ Assumed Max Input + Bias Voltage

??
I can't tell why you'd add half the input voltage to the gate voltage. I may just not understand what you're trying to do.

The classical method for doing bias is to decide some desired combination of voltages on the source and drain, then calculate a gate voltage to make those voltages "come true". The principle of superposition says that the input voltage is added to the bias voltage in proportion to the various impedances. This is fairly simple if you're using the fixed bias version with a string of resistors from V+ to ground, harder if you're using feedback biasing with a resistor string from the drain to ground.

In any case, you pick where you want the drain and source voltages to fall, then pick either the drain resistance or the current through the device. Picking the current is more straightforward to understand, and where you've started.

So we'll go to examples. You have a BS170 with yfs of 15ma/v. Pick drain and source voltages.  Note that hidden in this step is the requirement that you pick whether the source is grounded (Rs = 0) or the drain is at V+ (Rd = 0). But pick. Let's assume a 9V power supply to play with, and pick Vs = 1V, and Vd = 5V.

You've said you want the thing to bias at 1ma. I translate that to say that there is 1ma flowing with the input signal is zero volts peak to peak. We now know what our Rs and Rd are, and also the AC gain. There is 9V-5V = 4V across Rd and 1ma through it, so Rd is 4k. Likewise, the source resistor must be 1V/1ma = 1k. And gain is Rd/Rs in the absence of other feedback or bypassing setups, so the gain is 4.

Notice we have not said **anything** about what is going on at the gate, just what we want the output side to do.

The output from the drain has a limited swing. If the MOSFET is shut off, no current flowing at all, the drain voltage is 9V, because the output is pulled to +9V and the MOSFET acts like an open circuit. If the MOSFET is turned on as hard as it can be and acts like a short circuit, the output voltage at the drain can only swing down to 9V * Rs/(Rd+Rs) = 9* (1/5) = 1.8V.

So no matter what you do to the gate, the drain cannot swing outside the range of 1.8V to 9V with those conditions. If you want more output swing, you are limited to changing the ratio of the source resistor to drain resistor, generally by making the source resistor smaller, the drain resistor larger, and/or the idle current different. But once you pick those things, every possible value for drain (and source) voltage is determined. You can get back some of the AC gain by bypassing the source resistor with a cap. This makes the source voltage effectively fixed compared to the signal swing, and so you get a bit more swing on the drain than without it, but only for frequencies where the source cap holds the source fixed for a full cycle.

Notice we have not said **anything** about what is going on at the gate, just what we want the output side to do.

Notice we have not said **anything** about what is going on at the gate, just what we want the output side to do.

Now we look at what happens on the input side. You have not specified a biasing network schematic, so I'm guessing you're assuming the right DC bias voltage exists and will be supplied to the gate through some resistance. That's the simplest case.

VG = VT + ½ Assumed Max Input + Bias Voltage
= 2.0+1.5+0.06
= 3.56v

I do not follow what you're trying to do. The size of the input signal is immaterial for biasing. To bias the device, you have to set up the DC conditions as if the input signal was 0V, and in most RC coupled circuits, you assume that it's coupled in through a cap and can carry no DC component with it. Life gets harder if you insist on the input signal being DC coupled.
If there is an input coupling cap, you ignore the DC level of the incoming signal and set up your DC biasing network for the gate to be at the correct voltage with the input signal equal to 0V peak. Let's talk about that for a minute.

If you have your gate biased to the right DC level to make the drain and source be at your chosen DC levels, and an AC signal is imposed on top of the DC gate bias, then the input signal wobbles up and down around the DC bias voltage. For illustration, we'll change the preceding low gain circuit for one with Rd = 10K, Rs = 470R, and Id = 400uA. The drain sits at
9V - 0.4ma*10k = 9 - 4 = 5V and the source sits at 0.4ma*470 = 0.188V. The gain from the resistors is 10K/470 = 21.27, and since the raw transconductance gain is 10K*15ma/V or 150, the gain will be about 21. The total swing on the drain will be from 9V max to 0.4V min, or 8.6V peak to peak. It will be able to swing up by 4.0V and down by 4.6V, so the bias position is not quite perfectly in the middle for symmetrical clipping. But we have an example that kind of works.

How much change is needed on the input to slam the output from full off to full on? Easy; the gain is 21.27, so to move the drain up by 4V, you need the gate to go down by 4V/21.17 = 0.189V. To saturate the drain to the source, you likewise need 4.6V/21.27 = 0.216V.  Any signal that moves the gate up or down more than about 200mV is banging the drain against cutoff and saturation, and any signal bigger than that doesn't change the output voltage any.

As I typed that stuff, it kept nagging at me that you are trying to add half the assumed input to the bias voltage. It finally hit me that you may be trying to DC couple the drain of one stage to the gate of the next. Is that it? If so, you're going to need to post a schematic of what you're trying to do.

Iterated gain stages were popular at one time in the past, and they still form an interesting sidelight to the mainstream practice. But they are very tricky to get right. There is a real problem in iterated DC-coupled stages in that the Vt forms an offset voltage that quickly eats up the power supply available. It is ... possible... that you could get something to work for the unique conditions of a 9V supply and a 2-3V Vt MOSFET, maybe. Let's think about that.

An iterated MOSFET setup needs the drain of the MOSFET to be equal to the gate bias of the next stage. It is very tempting to say that this is the same as the gate bias of THIS stage, but wrong unless you can get very tightly matched MOSFETs, and monolithic matching may not be enough.

Again, you're going to want to set the output conditions of your stage first. Pick Vd and Vs, and the drain and source resistors (or current, which does the same thing). Then calculate the bias voltage the gate needs to make the drain-source conditions come true. This will be Vt plus some amount to make the dc idle current flow in Rd and Rs.

But now you need to make Vt plus a bit be equal to the drain voltage of the preceding stage, and the drain voltage of THIS stage be Vt plus a bit for the NEXT stage. As you've noticed, the "plus a bit" on top of Vt is a small fraction of a volt, and Vt is 2-3V. And that variation is what kills you. The variation of Vt is much larger than the "plus a bit" you need to to 100% of the change from cutoff to the DC idle condition on each MOSFET. So you wind up hand tuning each stage, and dying with thermal drifts. God forbid the power supply voltage wobbles by 100mV.

If you're looking for DC direct coupling of cascaded MOSFET stages, it gets very difficult at N=2, and the difficulty goes up by the Nth power of the gain and the variation of the Vt over the "plus a bit" bias voltage.

[Dylfish]

ok RG, I've had time to soak this in and lets see what i've got. Ill be honest, I think I'm missing something rather fundamental here.

I had initially added 1/2 the expected max so that when the guitar signal is on the gate, it would stop it from from saturating and cutting off.

If I have only 0.06v to play with and a 200 - 400mv signal to play with, How do I keep the entire signal from cutting off? (below is a drawing of how it's happening in my head, excuse the paint job)

0v p-p is "sitting"/Transposed on the DC bias for 1ma.



I have the same thoughts about issues with JFETS. having such a small VP and trying to keep the signal from going + or past the Vp.

[R.G.]

ok RG, I've had time to soak this in and lets see what i've got. Ill be honest, I think I'm missing something rather fundamental here.
...
If I have only 0.06v to play with and a 200 - 400mv signal to play with, How do I keep the entire signal from cutting off?

You can't.
Your voltage gain is simply too high. If an input of 0.06V sets your output in the middle of its range for DC purposes, then you can't input a signal that goes more than +/- 0.06V without causing the output to clip in either saturation or cutoff.

By choosing the currents and resistors on the output side and the transconductance (by choosing the active device) you've chosen a raw gain and a bias point. If the raw (that is, without negative feedback) gain is high enough that all by itself sets the biggest input which can be tolerated without clipping for that power supply.

Another way of saying this: if your power supply is (for instance) 9V and your gain is 25, the biggest input signal you could ever possibly hope to amplify without distortion is 9V/25 = 0.36V. If your gain is 100, the biggest signal you could accept in without distortion is 9V/100 = 0.09V. In practice, of course, the output swing is never the full power supply, so it's even less.

I think you're overspecifying the situation. There are only a limited number of independent variables. Once you set the power supply limits, voltage gain, and bias point, the input range is set too. If you specify the input range, bias point, and gain, the POWER SUPPLY has to change to keep from clipping. And if you have a fixed power supply and input range, the gain must change to keep from clipping on a certain sized input.

Let's talk about feedback. One way of looking at feedback is that it trades raw gain for polite, well-mannered lower gain. Another way more appropriate to your situation is that it uses external components and the raw gain to decrease both the overall gain and the input signal size as seen by the active device. A source resistor does this by raising the source voltage so the input voltage from gate to source remains small; in fact, it remains almost constant. Bypassing the source resistor defeats this by preventing the source resistance from following the gate accurately. It's possible to add feedback as a resistor from drain to gate and another resistor in series with the gate. This "inverting opamp" feedback reduces the signal swing on the gate by "cancelling" some of it with the drain swing. It also keeps the gate-source voltage small.

But again, I think you're caught in believing you can independently specify too many things.

[Dylfish]

Thanks RG. I've been doing some reading up on negative feedback so i hope I can get my head going around it soon.

I'm not sure if this is a silly question but I'm trying this in a sim, I have a JFET, Midpoint biased with a VP -0.65. I have put an O-scope either side of the scope and fed it a ~900mv signal, so I was expecting to see some clipping, even though minor. From what I can see it looks rather untouched? Is it a matter of it being such a small amount of input clipping that it's barely noticeable, and is more of a factor with a much larger signal?



and the waveform



P.s. Is it also due to the fact a sim can be somewhat unreliable opposed to real life?

Thanks, and sorry if you've already answered this =)

[R.G.]

Thanks RG. I've been doing some reading up on negative feedback so i hope I can get my head going around it soon.

I'm not sure if this is a silly question but I'm trying this in a sim, I have a JFET, Midpoint biased with a VP -0.65. I have put an O-scope either side of the scope and fed it a ~900mv signal, so I was expecting to see some clipping, even though minor. From what I can see it looks rather untouched? Is it a matter of it being such a small amount of input clipping that it's barely noticeable, and is more of a factor with a much larger signal?

Note that in your circuit, the signal at the source amounts to a source follower output, so it follows the input signal up and down. This is a form of negative feedback, and as a result, it decreases the gain of the JFET and increases its tolerance to input signal level.

To see this change, put a big capacitor across the source resistor.

[Dylfish]

Thank you very much sir 😄😃

[PRR]

> I was expecting to see some clipping, even though minor.

Watch the _DC_ Gate voltage. At zero input it is zero. At large (~~2V p-p) input it will go negative. C3 is charged-down by Gate clipping. This can be useful or it can be musically unpredictable.

BTW, don't make caps arbitrarily large. It makes SPICE run slower, and it masks some very real effects. In real life it tends to cost more, fit worse, and slow-down the turn-on. Have some general notion of a "proper" cap value for the circuit. Here we drive a 1 Meg resistor and the >200Megs of the Gate, which is 1Meg total. 0.01uFd into 1Meg will pass down to 16Hz. You might use 0.02uFd "just to be sure". but not 47uFd.

However your 932mV p-p is only 466mV peak. Source is at 326mV DC. The Gate is only going positive by 466-326= 140mV. 600mV sucks bad. 500mV sucks some. 140mV sucks hardly at all.

You have (apparently) ZERO source (input) impedance. (Yeah, 47uFd, which is zero-enough in a high-Z circuit.) The irresistable force WILL overwhelm the puny transistor and resistors. This is unrealistic. If you ever get a dead-ZERO source impedance, you may use a passive transformer for any voltage gain you need. However all real sources (even the 2-foot battery in my tractor) have some impedance. Tractor batt maybe 0.001 Ohms. Guitar 5K to 500K Ohms. General pedals <100K, but few will drive <1K happily. Put 50K in series with the input source to approximate a "typical" real-life source. When halfway happy, re-simulate with 150K, 5K, and zero, to see if it matters (ideally, very little).