using a 4053 to switch a clock pulse?

[Quackzed]

what i'm trying to do is this.
use a momentary to create a pulse 0v-9v-0v ish, and route this pulse through a 4053 to (A) a 4017 or (B) a 4013/4053 bypass setup.
so i'd have a separate stomp to switch this 4053 high or low (several 4053's actually) via a 4013 flip flop.
when its high the pulse will go through the 4053 to a 4017 clock input , when low it'll go to a 4013 clock input then to a 4053 to bypass like in the geofex article on bypassing with the 4053 mux...
so basically use one stomp to either control a 4017 to step through 4 different effects OR a 4013/4053 to bypass the selected effect.
    ok, so since the pulse is 0v (till pulsed) it will pop when the 4053 its going through is switched, fine. but will this popping trigger whatever clock input its connected to or switched to?  is the popping just a result of a fast change of dc in audio?
i can pull the clock inputs to ground when 'unselected' so can i switch a 0v signal into the 4053 to 2 different 0v biased points out of the 4053 without triggering the clocks on those 2 lines? or is the pop likely to be a spike that the clocks will read as a pulse?
i know, i know, this is a logic PITA. the reason is trying to minimize clock pulse wires to a remote box, hence the double duty scenario. sorry in advance if you get a headache reading this. 

[R.G.]

A CD4053 (or its CMOS brothers) will switch logic signals through it just fine, within its limits.

The limits are tied up in all that mess on the datasheets of the CD4053 and on the datasheets of the devices it is being used to drive, in this case a 4013 or another 4053 logic input.

You're about to get your first lessons in digital logic signals when considered as analog signals (which they are, just special analog signals).

Digital logic INPUTS are sometimes fussy about the signal that drives them. After all, digital circuits are really analog circuits, just designed in a way to minimize any signal between logic 1 and logic 0 levels.

1. A digital signal is a 1 if it's a higher voltage than the least positive up level (and there are some other terms for this, too). Each logic family may have different LPULs.
2. A digital signal is a 0 if it's lower than the most positive down level, ditto and ditto.
3. Some digital circuits are sensitive to HOW FAST the signal moves on their inputs, and further some are sensitive to how fast the leading edge of the signal moves, or the trailing edge of the signal, or both. These are the rise time and fall time specs on the datasheet.
4. Digital circuits are sensitive to how long the signal stays at its freshly changed state. Some of the datasheet numbers indicating this are the propagation delay times and hold time specifications on the datasheet. Some inputs are level senstive (what the signal level is matters most) or edge triggered (what matters most is the suddenness and speed of the transition, and of course, in which direction).
If you feed digital circuits signals that aren't quite right either in voltage level, timing, or speed, the circuit will do odd and inexplicable things.

A CD 4000 series switch looks like an open circuit or a few-hundred ohms resistor (that's on the datasheet). It also couples some charge into the switching channel when it switches. How big a VOLTAGE change this makes in the signal being switched depends on the impedance of the line the charge is being dumped into. Low resistance or high capacitance lines change little, high resistance and low capacitance lines change more. You have to know what you're driving; well, OK, or just be lucky.

If a few hundred ohms will pull your driven line to more than the LPUL or less than the MPDL for the input being driven, you're fine for static signal levels. If your control charge injection doesn't change the signal level enough to violate LPUL or MPDL, and doesn't happen at an unfortunate time, like on the exact nanosecond when the circuit is changing stage, you're fine. If your driven inputs are edge triggered, or level sensitive, you have to match the signal feeding them to what the input needs.

It's easy to get lucky with CMOS, as its inputs re relatively forgiving. In your case, you're probably fine. But there is plenty of hot water to get into.

One important note: EVERY CMOS INPUT MUST BE TERMINATED SOMEWHERE. It is incredibly frustrating to find that your bad results come from an open input "reading" the electrical charge of the atmosphere around it.

[Quackzed]

Thanks again man, i'm gonna cross refer some of this to the datasheets. try and get a solid understanding of the bounds i'm in trouble of breaking with this setup. that makes perfect sense though. hopefully i have some leeway via rise time for the 4017 'rising edge triggered i believe' may have to adjust pulldown size to accomodate speeds but i'm glad to have some room to move rather than a restrictive 1/2v bias vs. digital 0/1 problem...
as the pulse is not gonna be at the same time as the pulse routing switching, (at least not without me falling on my a$$)  then I should be able to keep everything happy. no floating digital inputs, gotcha.
really appretiate you taking the time to give such a thorough response!!!
 

[R.G.]

Part of that was pure education. You may well have no problems at all.

The rise time spec on the 4017 clock ( it's positive edge triggered) is specified as a maximum of 15uS at a 10V supply. The rise time of the OUTPUT of a CD4013 is about 100nS at a 10V supply. That's on the order of 150 times faster than a 4017 needs to work right. What you have to do is be sure that whatever else you glom onto the line between these two doesn't make things a lot worse. The CD4053 switch between them acts like a - call it 200 ohm - resistor. The output of a 4013 can pull its output to a valid logic level with an output load requiring 2ma of load current (I'm cheating and reading the data sheet as I do this; I don't have this memorized), so using the capacitive equation that I = C *dv/dt, we know I, dv and dt, so the maximum capacitance from all sources that will let this happen is

C = I*dt/dv = 2ma*15uS/dv.

"dV" is the difference between a valid 0 and a valid 1, and that's a minimum of 4V, so Cmax = 0.002*15E-6/4 = 7nF if I got the decimal point right. That's huge! So unless you're attaching your own slow-down capacitors, you're probably safe.

What really kills you in fast logic is getting a signal that reverses course a time or two right in the middle of a transition, or one that meanders slowly through the no-man's land of not-a-one-and-not-a-zero. What comes out of the end result is ... um, as they say, indeterminate. Might be anything.

Another thing that can get you is MML - Mickey Mouse Logic. This is the attaching of pull ups, pull downs, time stretching or speed-up caps, diodes and other junk to do some special timing or logic function. This is incredibly useful if you can manuver your way around the pits.

If you're at all interested in getting conversant with logic, go get a copy of the CMOS Cookbook by Lancaster. Used print copies are cheap on the used book sites and Amazon, and it's a whole quick education in itself.

[PRR]

CMOS Cookbook, Don Lancaster. Probably out of print but used copies are not expensive.

It would help to also have a TTL Cookbook, or RTL Cookbook, also from Don Lancaster. CMOS is mostly a better TTL which is a better RTL. Don covers some logic basics better in the older books, which were best-sellers, so he assumed readers would have the background.

[Quackzed]

actually, i'd only be using the flip flop  for the 4053 bypass, the 4017 would get the straight pulse.
so when switched to the 4017 side, its just the naked pulse of the transistor pulse 'driver', otherwise -with the 4013 in there it'd need two pulses, one to flip the flipflop 'high' 'rising edge' then one to flip it low (no change) then another press for another 'rising edge'.
so as long as i can get one transistor pulse driver to work into the 4017 and also the 4013, ill be ok. the 4013 should drive the 4053 'as is' from your article at geo. and i think the same transistor pulse driver will work with the 4017, its the pulldowns ill need on that 4053 that the pulse goes through that have me a little worried.
as is, the transistor pulse driver has a 10k in series with the output. if i used 10ks as pulldowns on the 4053's outputs i dont think it'll have enough voltage to work into either the 4013 or the 4017... but if i use a 500k or 1M , then those 'pops' may pulse the clocks?
oi' so i THINK 'problem' pinned down.
pulse into a 4053 (with a 4013 to keep it high or low) one side of that 4053 out to the 4017, the other side of that 4053 out to a 4013/4053 to bypass the effect. the trick being to keep that 4053s outputs referenced to ground so they're not floating without loading the pulse so much that the pulse wont drive the clocks and without loading them so little that the switching current of that 4053 'does' drive the clocks with switching junk... ?!?! oi, i do have a knack for complicating things!

[Quackzed]

ok, heres the flow i'm thinking of using...
bottom switch 4013 high= 4053 sends pulse to 4017. bottom switch  4013 low = 4053 sends pulse to 4013/4053bypass

[CodeMonk]

CMOS Cookbook, Don Lancaster. Probably out of print but used copies are not expensive.

It would help to also have a TTL Cookbook, or RTL Cookbook, also from Don Lancaster. CMOS is mostly a better TTL which is a better RTL. Don covers some logic basics better in the older books, which were best-sellers, so he assumed readers would have the background.

http://www.amazon.com/CMOS-Cookbook-Second-Edition-LANCASTER/dp/0750699434

Where I got my copy.
Careful though, mine was missing most of the TOC (Except the last page of them).
Good book though.