How do I scale this relay driver?

[Sage]

The uln2xxx is a transistor that pulls current into its output pin and down to ground. In the setup you've shown, the other side of the relay is at ground and there won't be any voltage for it to work on. Connect the (+) side of the relay coils to your V+, not ground. Then when the logic signal tells the driver to be "on", it will pull the (-) pin of the relay coil to nearly ground, and the V+ on the other side will let current flow in the coil.

Aha!  Okay, that makes sense.  I had thought the 2803 was passing voltage through, but it's the opposite.

Something I once got wrong - look up your relays and see if there is a preferred + and - pin on the coil. Some do and some don't, and if they do there is nearly always an internal diode or some such that makes the polarity matter.

Yeah, that's what I did -- I looked up the Panasonic TQ2-9V, since it's the lowest-current 9V relay available via Mouser.  I got the pins backward initially, though, so I'm glad I looked at it again.

And yes, there's a bit missing on the momentary switch side, but you already knew that. The idea there is to provide as good a single pulse to the "clock" pin of the flipflop as you can.

What do you mean?

Here's another mockup:


I used this toggle example as a template, but I don't know what the capacitors and resistors are actually doing here.  Why do I need a resistor between the data and /Q pins, and what does the resistance value signify, if anything?

Also, do I need to tie any of the unused pins on the ULN2803 to ground?  I remember this was an issue with the CD4069.

[Seljer]

In the linked schematic, C2 and R5 make a low pass filter, it basically adds a bit of 'delay' because C2 needs to charge up/down through the R2 before a new state presents itself to the input. This prevents accidentally re-triggering if your switch 'bounces' and with some types of digital chips, that setup with the direct loop from the output back to the input sometimes leads to funny behaviour .

R2 makes sure C1 is discharged (there is 0V over the capacitor) when the switch is not pressed. The clock input is usually at 5V through resistor R1. When you press the switch, you hook up C1 to ground, momentarily pulling the clock input low, C1 then quickly charges up and the clock input is back to 5V. The short blip in voltage that is presented to the clock input is enough to trigger a state change of the flip-flop.  Because it takes some time for the capacitor to discharge again it also adds some resilience to switch bounce.

[R.G.]

Aha!  Okay, that makes sense.  I had thought the 2803 was passing voltage through, but it's the opposite.

Another way of looking at the uln2803 is that it is like a row of NPN darlington transistors with all the emitters connected to the "ground" pin of the package. The input pins are the bases, the output pins are the collectors. So when you make the input/base pin high, the output/collector pin becomes a very low resistance to ground.

And yes, there's a bit missing on the momentary switch side, but you already knew that. The idea there is to provide as good a single pulse to the "clock" pin of the flipflop as you can.

What do you mean?
...
I used this toggle example as a template, but I don't know what the capacitors and resistors are actually doing here.  Why do I need a resistor between the data and /Q pins, and what does the resistance value signify, if anything?

Seljer is correct about the R-C used on the -Q to D pin paths. Logic circuits are deliberately designed to be as fast as possible - nanoseconds and pico seconds are the units used, not milli- or micro-seconds. In the linked circuit, the clock signal tells the flipflop to read whatever logic level signal is on the D pin, and force that onto the Q pin, while forcing the opposite onto the -Q pin. It also expects the clock signal to be nice and clean and square, one and only one rise and one fall.

Pushbutton switches are not nice, clean clocks. Mechanical switches bounce at the millisecond level. When you push the switch the contacts move toward each other, touch, bounce open from zero to many times, and finally settle at closed, until you release it. Generally the open process is not so bouncy, but it may be, depending on the mechanics.

Reading the 4013 data sheet, When the clock RISES, the logic level that was properly set up (that is, was stable for more than the setup time, 30nS for this chip at 10V supply) is transferred to the Q output no later than 130nS later. The logic level at the D input had to remain stable for t_hold nanoseconds after the clock rises to have this all guaranteed to work right.  The CD4013 is odd in that it does not specify a hold time at all, where most latches do. The linked schematic uses the resistor from -Q to D and the cap to ground from D to hold the -Q signal for some minimal amount of time, satisfying any "hold" time that the datasheet writer sloppily did not include. This is also some insurance against the pushbutton bouncing.

R1, R2, and  C1 are an attempt to clean up the switch bouncing as well. I have my doubts, but maybe it's fine. There will in general be some kind of R/C/D circuit on all the CMOS circuits that use manual pushbuttons to try to clean up the switch into a usable clock. In this one, the idea is that R2 discharges C1 to 0V across it, and then when the pushbutton connects, the clock is pulled low, as it was resting at high. This high-to-low change on the clock pin doesn't do anything. When the switch opens, the clock pin instantly goes high, and the logic level on the D pin is racing off into the circuit to the Q and -Q pins, taking 130nS to get there. 

If the pushbutton bounces, the clock rises many times because the switch opens many times. This would make for many "clockings" of data, making for an almost random state instead of the desired toggling, except that the RC network on -Q and D offer some relief in terms of sending the same data to D many times.

I have to confess, I cannot think of why R1, R2, and C1 are there. I don't think they help with bouncing much if at all. But then debouncing circuits are tricky - they are 100% "special cases" and designed to be so.  I use a different debouncing scheme on my CMOS input stuff, and the two-inverter  flipflop has the oddity that it needs no debouncing on the switch. But again, this may well work fine. Breadboard it first before you commit it to a board.

Also, do I need to tie any of the unused pins on the ULN2803 to ground?  I remember this was an issue with the CD4069.

Tying all unused inputs to either ground or V+ is a requirement specifically for MOS and CMOS circuits. The uln2803 inputs can be left open as long as you also leave the corresponding output pin open. This is not the most professional practice, but it does leave the pin open so you can later modify and adapt the circuit and I don't think it hurts in this circuit.

[Sage]

In the linked schematic, C2 and R5 make a low pass filter, it basically adds a bit of 'delay' because C2 needs to charge up/down through the R2 before a new state presents itself to the input. This prevents accidentally re-triggering if your switch 'bounces' and with some types of digital chips, that setup with the direct loop from the output back to the input sometimes leads to funny behaviour .

Cool.  So am I correct to assume that the value of R5 is in direct proportion to the amount of delay?

R2 makes sure C1 is discharged (there is 0V over the capacitor) when the switch is not pressed. The clock input is usually at 5V through resistor R1. When you press the switch, you hook up C1 to ground, momentarily pulling the clock input low, C1 then quickly charges up and the clock input is back to 5V. The short blip in voltage that is presented to the clock input is enough to trigger a state change of the flip-flop.  Because it takes some time for the capacitor to discharge again it also adds some resilience to switch bounce.

Wow, that's entirely backwards from how I was thinking of doing it, then.  Where are you getting 5V from?  I don't see the math.

I have to confess, I cannot think of why R1, R2, and C1 are there. I don't think they help with bouncing much if at all. But then debouncing circuits are tricky - they are 100% "special cases" and designed to be so.  I use a different debouncing scheme on my CMOS input stuff, and the two-inverter  flipflop has the oddity that it needs no debouncing on the switch. But again, this may well work fine. Breadboard it first before you commit it to a board.

Seljer's description suggests that the voltage is reapplied not when the switch is released, but when the C1 is fully charged.  If that's the case, then I think I understand why it's done that way.  By using the switch to pull the voltage to 0 instead of to apply voltage to the clock pin, and using the capacitor to reapply the voltage instead, you move the switch bounce to the low side of the clock, where it doesn't matter, because the 4013 only changes state when the clock is rising.  Then voltage is reapplied to the clock pin via the fully-charged capacitor, which has no bounce.  Clever!  But is that what's actually happening?

I'm not sure why you'd need both that and the R/C network between /Q and D... maybe it's just extra insurance?

Tying all unused inputs to either ground or V+ is a requirement specifically for MOS and CMOS circuits. The uln2803 inputs can be left open as long as you also leave the corresponding output pin open. This is not the most professional practice, but it does leave the pin open so you can later modify and adapt the circuit and I don't think it hurts in this circuit.

Just out of curiosity, what would be the more professional practice?

One more question: I'm assuming I'll be using 9V relays in this circuit just for simplicity's sake, but I know people use 5V and 3V relays all the time.  Is that just because of availability, or is there another reason?

[R.G.]

Seljer's description suggests that the voltage is reapplied not when the switch is released, but when the C1 is fully charged.  If that's the case, then I think I understand why it's done that way.  By using the switch to pull the voltage to 0 instead of to apply voltage to the clock pin, and using the capacitor to reapply the voltage instead, you move the switch bounce to the low side of the clock, where it doesn't matter, because the 4013 only changes state when the clock is rising.  Then voltage is reapplied to the clock pin via the fully-charged capacitor, which has no bounce.  Clever!  But is that what's actually happening?

I'm not sure why you'd need both that and the R/C network between /Q and D... maybe it's just extra insurance?

I don't know. If it works, it works. Try it on a breadboard.

Tying all unused inputs to either ground or V+ is a requirement specifically for MOS and CMOS circuits. The uln2803 inputs can be left open as long as you also leave the corresponding output pin open. This is not the most professional practice, but it does leave the pin open so you can later modify and adapt the circuit and I don't think it hurts in this circuit.

Just out of curiosity, what would be the more professional practice?

Grounding the inputs so the outputs can't wobble.

One more question: I'm assuming I'll be using 9V relays in this circuit just for simplicity's sake, but I know people use 5V and 3V relays all the time.  Is that just because of availability, or is there another reason?

Availability is a big one. Until the last couple of years none of the electronics distributors stocked 9V rated relays. I suspect the literal explosion of effects builders as a cottage industry gave them enough requests to start stocking the 9V variety. Before that it was 5V, 6V, or 12V mostly.

Picking a relay coil voltage depends heavily on what voltage you have available. If you are using a uC, those all run on 5V or less, so if you can run your relays on 5V, you don't need level translators to change from 5V to something bigger, and some low power relays can be driven from some uC pins directly. That's a PITA for 9V powered pedals. So it may also be for uC or other logic circuits' convenience.

Relay coils tend to need a  constant amount of power expended to move the relay - that is, the product of the voltage across the coil and the current through it. That's why you find relays rated in power: 100mW, 250mW, etc.; that's not the power the relay will switch, it's the power needed in the coil to switch it. A 12V relay tends to need half the current of a 6V relay coil if the rest of the relay is identical. So if you lower the coil voltage, you wind up increasing the coil current to keep about the same power expended on the coil.

[Sage]

Well, I got my parts, and used a breadboard to wire up one of the relays to the ULN2803 and the CD4013 just like my diagram.  I'm testing the switching via a bi-color LED.  I've run into an interesting problem...

When I apply voltage to the clock pin on the 4013, it changes state.  If I then remove the voltage and then apply it a second time, nothing happens.  However, if connect the clock pin to ground, then disconnect it, and *then* apply voltage again, it changes state again.  It's as though the clock doesn't return to low on its own.

Is this normal?  If so, how does one wire up the switch?  I intended to have a momentary switch connect the clock pin to +9V when pressed.  I assumed the clock would go high when the switch was pressed and then drop back to low when it was released, but that appears not to be the case.

[Seljer]

The 4000 series of chips are CMOS logic. The input stage is basically the gate of a MOSFET transistor. The gate of a MOSFET is basically a little capacitor. A capacitor won't discharge on it own, if you apply 9V to it and then disconnect the voltage source it'll stay at whatever voltage you charged it up to (watch this, it's rather intriguing https://www.youtube.com/watch?v=gloikp9t2dA ).

This is why you need to add a pull-down resistor (try something like 10kiloohms to 100kilohms) from the clock input to ground to make sure it goes back to 0V every time you release the switch. Or in the reverse situation, you add a pull-up resistor to the positive supply, and then have to switch connected between clock and ground the clock input goes down to 0V when pressed (and via the pull-up resistor goes back to 9V when released).

[Sage]

Ah, I get it.  I didn't realize the clock needed to be connected to both positive and ground; I sort of assumed the return to ground was done internally by the IC.  Thanks!

I added a 10k resistor between clock and ground, and it resolved the problem.  Now there's a new problem; looks like the single 2.7k resistor between D and /Q and the .1uF cap to ground aren't enough to resolve the switch bounce.  I'll try wiring it up differently and see if I can get a better result.

[Seljer]

2.7kilohms * 0.1micofarads = 270 microseconds
That is RC time constant -> the  time that it takes for the capacitor to charge up to 63% if you put a voltage step upon the them.

A switch can easily bounce around for a couple of 10millisecond or even more.

Try upping the 2.7k to something between 10k and 100k and see if it's any better.

[Sage]

Ah, thanks.  I figured the resistance value would affect the length of delay but I didn't know the exact calculation, so thank you.  Unfortunately, I tried 100k and didn't notice any discernable difference.  I'll try a higher value later today.

For the moment, I took another approach:



I replaced R5 with a jumper, and removed C2 entirely.  Then I implemented R1, C1, and R2 as shown above.  For some reason, this works.  The R5/C2 combo appears to be unnecessary.  Do you have any idea why both R/C networks are present in the above example?  Are they supposed to work together somehow or are they just redundant?

Something that occurred to me... would a momentary SPDT switch obviate this entirely?  If I connected the common pin on the switch to the clock, then connect one side to ground and the other to V+ then the bounce ought to be moot, right?  Is there any downside to that idea?

[R.G.]

You're running into some of the picky little things I alluded to earlier.

Logic chips are specified in terms of the signal levels that qualify as high and low for the logic family, and in terms of how long before or after a signal achieves a valid high or low that things both *CAN* and *MUST* happen. And these timings are usually specified in units of nanoseconds for CMOS.

CMOS is a little funny for people used to non-MOS  circuits. The input of a CMOS gate is as near an open circuit with a small capacitance to ground as any electronics usually gets. That's why the unused inputs of any CMOS part must be tied either high or low. If you don't do this, it will wander around between high and low based on the voltage in the air around it.

The 4013 is a standard CMOS input part, and as such the clock is required to have maximum rise and fall times. If the clock rises or falls too slowly, the internal logic may go off wandering through the weeds while the clock is in the indeterminate region between high and low. That's good for logic operations, but bad for people who want to hook external switches to it.

And it's one reason that hooking up switches to normal CMOS always involves resistors, caps and/or diodes to try to make the signal look edible to the CMOS input that we want to eat the signal and react well to it.

CD4013s used for toggle flops will (in my experience) work OK once you find the certain combinations of R-C-D to make them think they're getting an OK input. Otherwise, they will be erratic.

At the risk of being repetitive, that's some of the reasoning that led me to adopt the two-inverter toggle flop as a standard. The Rs and Cs that make it work right are very forgiving in value. These things nearly always work first time, every time. It's possible to get them wrong,  but most of the time, they just work.

[Sage]

The input of a CMOS gate is as near an open circuit with a small capacitance to ground as any electronics usually gets. That's why the unused inputs of any CMOS part must be tied either high or low. If you don't do this, it will wander around between high and low based on the voltage in the air around it.

The 4013 is a standard CMOS input part, and as such the clock is required to have maximum rise and fall times. If the clock rises or falls too slowly, the internal logic may go off wandering through the weeds while the clock is in the indeterminate region between high and low. That's good for logic operations, but bad for people who want to hook external switches to it.

So this would rule out my momentary SPDT switch idea, then?  I figured that if the common terminal of the switch was connected to the clock pin on the 4013, the bounce would be nullified because it's bouncing between the +V and floating (which doesn't change the state of the clock) -- as opposed to the SPST with the pulldown resistor to ground, which bounces between +V and Ground.

CD4013s used for toggle flops will (in my experience) work OK once you find the certain combinations of R-C-D to make them think they're getting an OK input. Otherwise, they will be erratic.

At the risk of being repetitive, that's some of the reasoning that led me to adopt the two-inverter toggle flop as a standard. The Rs and Cs that make it work right are very forgiving in value. These things nearly always work first time, every time. It's possible to get them wrong,  but most of the time, they just work.

Yeah, those 2-inverter T-flipflops are looking better all the time.

That said, I'm pretty happy about the R1/C1/R2 setup in the example above.  It works reliably, it protects against the switch being held down too long, and it effectively combats switch bounce by confining its effects to the falling edge of the clock, which doesn't affect anything.  I really want to understand better what the values of these components signify.  What happens if I raise/lower the values of R1 or C1?

[Sage]

Well, I was wrong.  The R1/C1/R2 setup I posted above does work most of the time, but every once in a while it doesn't.  This wouldn't be a problem except that what I've designed requires two or three of these relays to activate at the same time via a single dpdt or 3pdt momentary switch, and every now and then they get out of sync when one latch activates and the other does not.  I don't think it's the switch.  I sure hope it's not the switch.

There's another solution out there that looks a bit more solid:


This uses the other half of the CD4013 as a debounce method by hooking up a momentary spdt to the set and reset pins on one side.  The other side does the flip-flop work.  I just send pin 13 in the image above out to the uln2803 to control the relay.  I've laid this out on a breadboard and it seems to work.  While technically this doesn't really scale any better than the original hex inverter idea, it does use fewer components (just two resistors per IC) and is easily duplicated.  Hopefully this will prove more reliable than my first attempt.