Question on how the SAD1024 is used in the Electric Mistress

[DrAlx]

I've just taken a look at the schematics for the original and Deluxe versions on the Electric Mistress Mystery page.

http://www.metzgerralf.de/elekt/stomp/mistress/index.shtml

Both delay lines in the SAD1024 are used but it doesn't seem to be using parallel multiplexing as I originally assumed.
The two delay lines seem to sample the audio at exactly the same time (i.e. no interleaving).
I can't see how this is any better than using just one of the delay lines.
I mean wouldn't the amount of noise and clocking glitches be just the same, or am I missing something here?

And why wouldn't you want to use parallel multiplexing anyway.  Does aliasing from low clock rates give any desirable effects?

[Fender3D]

Actually they are using parallel multiplexing, EH simply used outA (inverted) and outB instead of inverting clock phases;
as suggested in datasheet other pins are connected to Vdd and GND.

PM will give a better sampling rate, achieving a lower signal distortion and you may use lower steep filters @ single BBD's same performance.

[DrAlx]

Actually they are using parallel multiplexing, EH simply used outA (inverted) and outB instead of inverting clock phases;
as suggested in datasheet other pins are connected to Vdd and GND.

PM will give a better sampling rate, achieving a lower signal distortion and you may use lower steep filters @ single BBD's same performance.

I saw how they combined the outputs but don't see how that is parallel multiplexing...

Correct me if I'm wrong, but only the very first capacitor in a delay line does the actual sampling.
It starts to "read" the audio signal when its clock 1 goes high, and starts to "write" into the next bucket when its clock 2 goes high.
I'll call this "sampling when clock 1 is high" because nothing is sampled when its clock 2 is high.

The SAD1024 datasheet shows a parallel multiplexing example with the clock lines swapped between the two delay lines.
I take that to mean that the two delay lines are similar in the sense that they both "sample when their clock 1 is high".
Hence the clock lines have to be swapped to parallel multiplex, with one delay line reading while the other delay line writes.
My point is that it's the input of the delay line that is important, not the output.

If you don't swap the clock lines then both delay lines do exactly the same thing as each other.
So the times when outA switches off coincides with the times when outB does.
Same goes for their complementary ("inverted") outputs.
They had to mix the outputs from the two lines in they way they did to avoid the gaps.
That's just "gap filling" at the output, and no different to mixing outA and outA.
No extra sampling is going on at the input.

[Fender3D]

...If you don't swap the clock lines then both delay lines do exactly the same thing as each other.

yes they do,
but outA has 1 more stage,
then data @ outB will be 1 clock "step" ahead outA, it is the same as "retarding" sampling 1 clock cycle.

[DrAlx]

...If you don't swap the clock lines then both delay lines do exactly the same thing as each other.

yes they do,
but outA has 1 more stage,
then data @ outB will be 1 clock "step" ahead outA, it is the same as "retarding" sampling 1 clock cycle.

Yes, that's just the "gap filling" I describe.
The data in outA and outA are just consecutive buckets in the delay line, and so contain consecutive samples at the sample rate of the input.  i.e. both those buckets were sampled when clock 1 was high.
To parallel mux you have to take samples when clock1 is high and when clock2 is high.  The EM does not do that.

Actually ignore all of the above.  I need to read the datasheet properly!

[Tony Forestiere]

I know this is not directly answering your question, but some food for thought?

https://dl.dropboxusercontent.com/u/3173950/SAD1024%20Blocks.PDF

[DrAlx]

OK, I've looked at the diagram of the SAD1024 delay line in the datasheet.
As first I thought I had misunderstood something because it looked different to the delay line in the MN3207 (which I am familiar with), so I crossed out my reply above because I thought the SAD1024 must be doing something strange that I had not considered.
On closer inspection though it just confirms what I'm saying.

The delay lines for the SAD1024 and MN3207 essentially follow the same pattern of capacitors preceded by FETs that are gated by an alternating pattern of CLOCK1 and CLOCK2.  (The very first cap in the SAD1024 is gated by CLOCK1, while in the MN3207 it is by CLOCK2).

The SAD1024 output stage seems more complicated at first because the last few capacitors from gate 510 onwards are "duplicated" (there is a set for one output and a set for the other with an extra capacitor).  The MN3207 also has an extra capacitor for one of its two outputs, but it does things in a more straightforward way and avoids duplicating the last few capacitors in the delay line.

The end result is the same.  The BBD outputs are simply providing buffered access to consecutive capacitors, and therefore they can be combined to give an output with no gaps.  Remember that if you look at any consecutive pair of capacitors in the delay line, then only one of them will be charged at any instant in time.  e.g. when CLOCK1 is high the odd capacitors have the data, and when CLOCK2 is high the even ones do.  

In the case of the SAD1024, a piece of data that was sampled at the BBD input (when CLOCK1 was high) appears some time later on the cap to the right of the FET numbered 512 when CLOCK1 is high again.  When CLOCK1 next goes low (and CLOCK2 is high) this same piece of data appears AGAIN but this time on the cap to the right of the FET marked 513.
The fact that the data comes out like this in two repeated chunks at the two outputs is NOT extra sampling!!!
It is just a result of the fact that we have pairs of consecutive capacitors, and the sampled data is stored on only one of them at any instant in time.

In any case, my main point still holds.  The sampling takes place at the input of the BBD and only occurs when one of the two clock signals is high, and not the other.  That's clear from the diagram of the delay line.  If you want to parallel mux, you must take the samples when the other clock goes high. The EM is definitely NOT parallel multiplexing!!!

[StephenGiles]

......and it still sounds great!!!

[DrAlx]

I think it sounds great too.  I just can't see any advantage to using both delay lines in that way.

This is from the SAD1024 datasheet...

"Multiplex operation is generally preferable only when operating at high sample frequencies, as a means of reducing individual section rates."

I read that as "if you need a very high sample rate, then use parallel multiplexing to keep the clock rates down".
Then it says...

"For sample rates of 200 kHz or below, other limitations generally favor serial operation."

It doesn't say what those limitations are though.

The original EM can sweep down to the 10ms to region, so using just 512 stages means the sample rate goes down to 25 kHz.  So the full audio bandwidth is not sampled properly, and all signal above 12.5 kHz (mostly harmonic content) gets aliased down to stuff below 12.5 kHz.

Parallel mux is one way to solve that "problem".  The other is to make a single 1024 stage line and clock things at double the rate.
Maybe a longer line at higher rate is less noisy too?

None of the above explains why the EM uses both delay lines for no apparent gain over using just one.
Is there some "reliabilty" reason.  i.e.. if one delay line gets fried for some reason, you at least get something out of the other, albeit with gaps in the output signal.

[Fender3D]

...The EM is definitely NOT parallel multiplexing!!!

I looked again at both datasheet and schematic...
you're right EM ain't parallel mux... (perhaps it might be a nice song title  )...

lol I've always thought it was

Then your question is legit:

why the EM uses both delay lines for no apparent gain over using just one.

...back then many SADs were easily prone to fail

if one delay line gets fried for some reason, you at least get something out of the other, albeit with gaps in the output signal.

as reported by other members EM works even with 1 dead line...
I would add the easier PCB routing without criss-crossing the clock lines...

[armdnrdy]

So...the BBD line can be accomplished with a SAD512.

[DrAlx]

So...the BBD line can be accomplished with a SAD512.

I would think so. 
I just found this page which provides a clue to the weird configuration...

http://www.handmades.com.br/forum_antigo/index.php?topic=8571.10;wap2

Translated from Portugese to English there is this intriguing comment...

"In the case of Electric Mistress Flanger, I suggest using the same SAD1024 or adapt it to the MN3010. This is true because this circuit uses one of the unusual settings of SAD1024 / MN3010, which provides very low residual noise clock."

If that is correct then how?
Does connecting one of those unused outputs on a delay line to Vdd (as they say on the data sheet) cause the clock glitch on the used output to be lower?

[anotherjim]

Hmmm... Maybe "half faulty" SAD1024 could be had cheaper from Reticon than the knowingly half faulty version that had whichever good half bonded to consistent pins. The SAD1024 that EHX got, could have either half faulty, so they use a config that doesn't care.

[DrAlx]

I just did a quick experiment (on a 3207) to see if it makes any difference how you handle an unused BBD output.
In one case I tied it to Vdd and in the other I terminated it with 100k to ground.
I measured the clock glitch on the used output and found no significant change in its size.
It's what I was expecting but wanted to make sure.  The SAD1024 may be different but I doubt it.

I am thinking Jim may be right. There's no point attempting a parallel mux scheme if you expect lots of your chips to be half-working or likely to fail.  They could have wired things for parallel mux of course, but then maybe there would be a more obvious difference between a fully working BBD and a half-working one due to the different sample rates.

I wonder how many EMs out there have half-working BBDs and how many people would even notice if they were.  With one delay line not working, there's just one BBD output and no second output to balance it against, so clock noise will be worse.   That's more mojo in the case of the EM

[Govmnt_Lacky]

Isn't there a BBD output "balance" trimmer on the outputs of the SAD in the Deluxe EM? If one of the delay outputs went dead on those, wouldn't someone have to crank that trimmer towards the "working" side?

[DrAlx]

Interesting point.  I think it depends on how the delay line is damaged.
I can think of a few examples...

Example 1:  The final FET at the bad output no longer switches on so the bad output is always floating. So one end of the trimmer is floating and the trimmer has practically no effect on either glitches or amplitude of the signal at the good output.

Example 2:  The final FET at the bad output is permanently on so there's always a path from the bad output to the drain.  In that case the bad output actually interferes with the sampled audio coming out of the good output (because it does not float when the good output is on).   The trimmer would effect the amplitude of the signal.

Example 3:   The final FET at the bad output gets clocked OK, but something else in the delay line stops the sampled data going through.  So you end up with clock glitches at the bad output but no useful signal to fill in the gaps of the good output.  The trimmer won't have much effect on glitches or signal.

I can see Example 2 being a problem.  Not so much the others. Can't say what is the most likely behaviour.

[Fender3D]

So...the BBD line can be accomplished with a SAD512.

EM uses 512 stages, parallel multiplex or not...

I can see Example 2 being a problem.  Not so much the others. Can't say what is the most likely behaviour.

FETs usually open...
IMO
EH'd have better connect outA and outB (and outAwith outB ) toghether, they would achieve higher signal and potentially lower noise...

[12Bass]

An old topic... but I'm wondering whether parallel multiplexing can actually be done either by flipping the phase of the clock on one section of the SAD1024 or simply by taking the sample from the alternate output on one section with both sections using the same phase clock?  In other words, in terms of multiplexing, what practical difference does it make if we combine output A and output B' using the same phase clock?  Surely the result of that sum is not the same as combining output A and output B with the same phase clock, because the signal output at B' arrives one half a clock cycle later than the output at B. 

Forget about output A for a moment so we can focus only on what happens to the phase of the signal that is produced at output B and output B'.  If we assume that both A and B delay sections share the same phase clock, is taking the output at B' not effectively providing the same signal as using the opposite phase of clock and taking the output at B instead?  It would seem that the output at B' with an in-phase clock would be practically the same signal as the output at B with an inverted-phase clock.  If so, then both methods are essentially equivalent, and both allow the signal to be reconstructed by combining two samples per clock cycle. 

The only caveat that occurs to me is that the initial samples are taken at the exact same time with the in-phase clock setup and one half of a clock cycle later with the inverted clock setup, but I'm not sure this matters.  However, because we are combining output A and output B', we are combining one sample when the clock is high from output A and another sample when the clock is low from output B', one half of a clock cycle later.  Thus, either way we are still combining two samples at the output of the two delay sections which arrive on opposite clock phases, just as in a parallel multiplex scenario using inverted-phase clocks for each half of the delay chip.

Logically, this seems to make sense.  Perhaps I'm missing something....

[DrAlx]

As explained up the thread, the sampling process takes place at the BBD input and only when the clock pulse goes high.
For parallel mux the two BBD lines need to take samples at different times.  Therefore the lines MUST use opposite phase clock to each other.

Lets say you have this input sequence of letters to a delay line

Code Select Expand


Input <---    ABCDEFGHIJKL


Delay line 1 samples these letters at its input: A C E G I K.
The other letters are not sampled (because the delay line only samples when its clock goes high)
The sampled letters appear at the two outputs of the delay line like this

Code Select Expand


A x C x E x G x I x K x    <----  Line 1 Output 1
x A x C x E x G x I x K    <----  Line 1 Output 2


The sampled letters come out with gaps "x" between them and you need to combine the two outputs to fill the gaps.
giving you this

Code Select Expand


A A C C E E G G I I K K    <----  Line 1 (Output 1  + Output 2)

So the sample rate has not been high enough to capture the input letter sequence.

For parallel mux you need a second delay line to sample the letters B D F H K L
and to do that the second line must use opposite phase to the first.  As a result the letters appear at its output like this

Code Select Expand


x B x D x F x H x J x L x   <----  Line 2 Output 1
x x B x D x F x H x J x L   <----  Line 2 Output 2

Note that the Output 1 here now starts with a gap "x" rather than a letter !!! (because the phase was swapped).

So if you want to combine outputs from both delay lines to get the sequence ABCDEFGHIJKL
you need to take Line 1 Output1 + Line 2 Output 1 so the gaps are properly filled.

[12Bass]

Yes, I see that there is a huge problem if we are sampling unrelated digital values over time (e.g. ASCII characters). 

But in practice, the two delay lines A and B will be taking samples of continuous analog waveforms and the voltages we sample in those waveforms will likely change very little over half of a clock cycle provided the sampling frequency is high enough.*  So, instead of missing the sample data completely as in the example above (A,C,E,...), we are getting an analog sample value from the B' output which is a slightly incorrect voltage representing a slightly incorrect point on a continuous waveform.  In essence, it seems that instead of properly doubling the sampling rate as in proper parallel multiplex operation, we are instead getting double the samples combined at the output of A and B', but with some added analog sampling error when reconstructing the waveform. Also, perhaps this method allows similar SNR and cancellation of clock noise, and that is what matters most?

*I'm thinking there are some deeper aspects of sampling theory which may come into play here which I do not fully understand.  Wondering if the pseudo parallel multiplex method results in smearing of the sound at frequencies approaching Nyquist or other sorts of distortion?  My A/DA clone employs proper parallel multiplex and the delay path sounds surprisingly high fidelity.

BTW, I replied to this thread because it struck me as a puzzle and sometimes I like to try to solve puzzles.