A few questions re Ibanez switching

[disorder]

http://www.electrosmash.com/images/tech/tube-screamer/tube-screamer-jfet-bypass-switch.png

First question is... what purpose does D6 and R29 serve? I'd imagine R29 is just current limiting to protect which transistor is currently on. But what about D6? It seems to be a standard small signal silicon diode. Does it help with the base biasing of the transistors? The way I see it that diode keeps the emitters at ~0.6V above ground then the base will now need ~1.2V before it starts to turn on.

Second question... In RG's Technology of JFET switching he shows a setup where the toggle control three switches, SW1+SW2 are controlled together and exist at the input and output of the effect. SW3 state is inverse to the other two and it switches your dry signal line. The Ibanez schematic above has a two switch setup that has one switch at effect output and one on the dry line. Is there any benefit to having the extra switch at the effect input? Perhaps it presents less of a load on the input buffer?

http://www.geofex.com/Article_Folders/bosstech.pdf

[R.G.]

First question is... what purpose does D6 and R29 serve? I'd imagine R29 is just current limiting to protect which transistor is currently on. But what about D6? It seems to be a standard small signal silicon diode. Does it help with the base biasing of the transistors? The way I see it that diode keeps the emitters at ~0.6V above ground then the base will now need ~1.2V before it starts to turn on.

It enables the momentary switch toggle signal to trigger the flip reliably.

Second question... In RG's Technology of JFET switching he shows a setup where the toggle control three switches, SW1+SW2 are controlled together and exist at the input and output of the effect. SW3 state is inverse to the other two and it switches your dry signal line. The Ibanez schematic above has a two switch setup that has one switch at effect output and one on the dry line. Is there any benefit to having the extra switch at the effect input? Perhaps it presents less of a load on the input buffer?

Yes. There are conditions where the effect circuit is not benign when it's driven with signal while bypassed, and this can cause oscillation or bleeding of effected signal into the bypassed signal. It keeps things quieter.

Some effects circuits actually need their inputs AC-grounded for quietness reasons, which is yet another permutation.

[disorder]

It enables the momentary switch toggle signal to trigger the flip reliably.

By virtue of changing the turn on voltage of the transistors?

[R.G.]

By virtue of changing the turn on voltage of the transistors?

That's one way to look at it. Another is that the emitters are raised above ground so the bases can actually be pulled below the emitters for a very short time.

[disorder]

That makes sense. Pulling base to ground is more surely going to turn off a transistor who's emitter is at least ~0.6V above ground.

I've noticed one more grey area on the Ibanez switching schematic. There's an extra diode and resistor on the gate of the Q4 JFET. I understand what R16/C11/D3 are doing on the other switch but the arrangement at Q4 has me stumped.

[duck_arse]

I've been looking at those sort dia's recently too. I'm pretty sure RG would say the extra diode means Q5 collector going high will reverse bias D11, so the parallel resistor does the C12 charging, whilst when Q5 C goes low, the now forward biased D11 will allow (the probably much lower value) R47 to discharge the cap, so providing one short and one long switching time for the fet.

as for which one is long and which is short, and why the difference, I'm not sure what he'd say.

[disorder]

I see it now. And yes, it's hard to say which way is faster and which is slower as the resistor values aren't labeled.

I've been playing around with a spice sim of the actual JFET switches themselves. The switch goes from ON to OFF at 1mS which is where the cursor is on the graph. Keep in mind I've also included the RC time constant circuit as well so that's adding some delay. You can see how the negative peaks of the input signal come through first. Presumably because they are decreasing the source voltage bringing it closer to the (now increasing) gate voltage. So that must be where we get closer to leaving Vgs(off) territory. VF1 = gate voltage VF2 = output VG1 = input.

http://i.imgur.com/oV6uf5r.jpg
http://i.imgur.com/w8dif5J.jpg

[duck_arse]

I have an Ibanez something circuit, it looks like a big muff copy, marked "MP-D01001A". it shows both switch-fets with the twin diode caper, the blocking series are 1M and the parallel bypassers are both 3M3. there is another circuit of something here that I can't lay my hands on, only has one of the twin diode blocker switch fets. catchy name, huh?

[edit :] I was wondering if RG would tell us, if we add an R//C between the second and third inverters in one of his inverter bypass circuits, would it provide the same delay//drag function as the blocker set-up shown here. this is only a very slight sidetrack ....

[bloxstompboxes]

I have an Ibanez something circuit, it looks like a big muff copy, marked "MP-D01001A". it shows both switch-fets with the twin diode caper, the blocking series are 1M and the parallel bypassers are both 3M3. there is another circuit of something here that I can't lay my hands on, only has one of the twin diode blocker switch fets. catchy name, huh?

[edit :] I was wondering if RG would tell us, if we add an R//C between the second and third inverters in one of his inverter bypass circuits, would it provide the same delay//drag function as the blocker set-up shown here. this is only a very slight sidetrack ....

Sounds like your talking about this one duck. If you have everything laying around somewhere, you might get a bit of money for that.

http://fuzzcentral.ssguitar.com/schematics/OD850.gif

[duck_arse]

ahh, sorry, I meant "circuit diagram", not some expensive pedal.

[antonis]

Pulling base to ground is more surely going to turn off a transistor who's emitter is at least ~0.6V above ground.

Not valid for p-n-p BJTs..

[R.G.]

I see it now. And yes, it's hard to say which way is faster and which is slower as the resistor values aren't labeled.

Not really. The way with the diode "on" will always charge or discharge the cap faster than the way with only one resistor conducting, as one way there are two resistors conducting, and two resistors are always a lower resistance that either one. If *two* diodes were used, one each way, you could change the charge and discharge times indepenedently with the two resistors, although this is unnecessary complication.

I've been playing around with a spice sim of the actual JFET switches themselves. The switch goes from ON to OFF at 1mS which is where the cursor is on the graph. Keep in mind I've also included the RC time constant circuit as well so that's adding some delay. You can see how the negative peaks of the input signal come through first. Presumably because they are decreasing the source voltage bringing it closer to the (now increasing) gate voltage. So that must be where we get closer to leaving Vgs(off) territory. VF1 = gate voltage VF2 = output VG1 = input.

Yep. The signal itself modulates the Vgs for a fixed Vgate.

I was wondering if RG would tell us, if we add an R//C between the second and third inverters in one of his inverter bypass circuits, would it provide the same delay//drag function as the blocker set-up shown here. this is only a very slight sidetrack ....

Depends on a lot of things, like the inverter gate characteristics. CMOS gates have not-very-well specified transition points, and in the middle between "0" and "1" on the inputs, their gain changes on the way. Then there's the response of the switch element itself. If you can point to a typical schematic you're meaning, I can do a better job of explaining.

[duck_arse]

in the above, if the R//C was between the pin3 and its 100k resistor, was where I was thinking. switch elements would be the standardish 1M//47nF//diode//fet gate, for eg, the ibanez jfet switch setup.

[R.G.]

Ah. I understand.

Yes, putting a delay circuit there would let you insert a delay between the time the 7-6-5-4 flipflop changed state and when pin 2 changed.  Using an R-C would slow down both turn on and turn off, as the input levels on CMOS are mostly symmetrical. Using diodes and more than one resistors would let you do two different delays.

There are issues with this. It's best done with a Schmitt trigger gate like the CD40106 because the snap action will prevent the 3-2 gate from dithering around in the middle between 1 and 0 because of stray capacitance and such. Ordinary gates like the 4049 and 4069 may wobble in the middle or even oscillate for a bit, potentially causing the 4053 much confusion about whether to be on or off.

Also, it won't do much to how fast the 4053 switches. The 4053 is internally buffered, so when its input get high(low) enough, it changes state. It doesn't switch noticeably more slowly because the input control signal is moving slowly. And it too may wobble or squark when it's control signal is in the middle.

[PRR]

> may wobble or squark

Can't we stop that with a sfermion superpartner ?

http://en.wikipedia.org/wiki/Stop_squark

[duck_arse]

perhaps when cern next throws the switch (this week?), we'll all have squarks. or dark matters.