Try to understand Jfet Distortion and want to design my own.

[nguitar12]

I saw Jfet Distortion is relatively simple and so I decide to study the principle behind so that it can help me to debug my build or even make my own design. However I can't find and information about that.



http://www.runoffgroove.com/eighteen.html

Take above circuit as an example.
1. What is the purpose of the cap and resistor between the source and he ground?
2. What is the purpose of the cap and resistor between each gain stage?
3. Why two set of 15k/22n cap and resistor couple is placed at output?

Sorry for many question but if some one can give me some information on this will be greatly appreciated.

[armdnrdy]

Look up JFET Mu amp.

R.G. has written quality pieces on the subject.

[amptramp]

Answered in order as numbered:

1. The JFET is a relatively large-tolerance device when it comes to bias.  One way to accommodate different levels of gate-to-source voltages is to bias the source with a resistor.  The source has current flowing through it until it reaches a value that provides a positive bias on the source with respect to the gate that will keep the current within usable limits.  If the transistor has high gain, more current will flow and the source will go higher, reducing the gain.  If the device gain is lower, the opposite will happen.

The capacitor across the source resistor reduces the impedance at high frequencies so that the gain is not reduced as much as it would be with just the resistor.  The source voltage (without the capacitor) would follow the input voltage and reduce the gain.  With the capacitor, the resistor provides the correct DC bias for the FET but does not reduce the circuit gain.

2. The capacitor blocks DC voltage but allows AC to pass through so the DC drain voltage of the previous stage does not affect the gate voltage of the next stage but the AC signal still passes through.  The resistor is required to set the average gate voltage of the next stage.  Think of the capacitor this way: you have wires connected to two parallel plates.  If a wire goes positive on one end, the electrons move out of the plate it is connected to into the wire and leave a lack of electrons on that plate.  This makes it positive, which attracts electrons on the opposite plate, causing the wire attached to it to go positive.  But there is no net flow of electrons, so DC voltage is kept separate and only AC gets through.

3. Any distortion creates higher-harmonic components that may sound harsh, so this forms a lowpass filter that reduces the amplitude of components above about 4 KHz in this case.

[amptramp]

These are not mu amp stages, which require two FET's per stage.  Your schematic shows three normal grounded-source stages.

A mu amp has two FET's in series with the lower one connected like the ones in the schematic you have given but the upper FET source connected to the lower drain through a resistor and the gate of the upper FET connected to the drain of the lower FET.  If the input voltage goes up on the lower FET, its drain current goes up, increasing the negative bias on the upper transistor and forcing its current to be reduced.  Since the two transistors are in series, any difference in current goes to the load.  It is possible to design a mu amp distortion that has too high a load impedance, forcing the output to limit against the upper or lower power rails, but the design you have shown is not that.

[nguitar12]

Answered in order as numbered:

1. The JFET is a relatively large-tolerance device when it comes to bias.  One way to accommodate different levels of gate-to-source voltages is to bias the source with a resistor.  The source has current flowing through it until it reaches a value that provides a positive bias on the source with respect to the gate that will keep the current within usable limits.  If the transistor has high gain, more current will flow and the source will go higher, reducing the gain.  If the device gain is lower, the opposite will happen.

The capacitor across the source resistor reduces the impedance at high frequencies so that the gain is not reduced as much as it would be with just the resistor.  The source voltage (without the capacitor) would follow the input voltage and reduce the gain.  With the capacitor, the resistor provides the correct DC bias for the FET but does not reduce the circuit gain.

2. The capacitor blocks DC voltage but allows AC to pass through so the DC drain voltage of the previous stage does not affect the gate voltage of the next stage but the AC signal still passes through.  The resistor is required to set the average gate voltage of the next stage.  Think of the capacitor this way: you have wires connected to two parallel plates.  If a wire goes positive on one end, the electrons move out of the plate it is connected to into the wire and leave a lack of electrons on that plate.  This makes it positive, which attracts electrons on the opposite plate, causing the wire attached to it to go positive.  But there is no net flow of electrons, so DC voltage is kept separate and only AC gets through.

3. Any distortion creates higher-harmonic components that may sound harsh, so this forms a lowpass filter that reduces the amplitude of components above about 4 KHz in this case.

Thanks for your detail explanation. Referring to question one. I find that the value of the cap and resistor between the source and he ground can be quite different, Please look at the following circuit.



As you can see the top "treble" gain stage have a 2.7k/680n couple while the bottom "normal" gain stage have a 820r/330uf couple. How those values is calculated/determined ?

[midwayfair]

As you can see the top "treble" gain stage have a 2.7k/680n couple while the bottom "normal" gain stage have a 820r/330uf couple. How those values is calculated/determined ?

Read these to start:
http://en.wikipedia.org/wiki/RC_circuit
http://en.wikipedia.org/wiki/Low-pass_filter
http://en.wikipedia.org/wiki/High-pass_filter
http://en.wikipedia.org/wiki/Band-pass_filter


Bookmark this: http://sim.okawa-denshi.jp/en/Fkeisan.htm

[armdnrdy]

These are not mu amp stages, which require two FET's per stage. 

Understood.

I was leading the OP down the Mu amp trail in response to the title of his thread.

"Try to understand Jfet Distortion and want to design my own."

I feel that some of the best sounding distortion/overdrive FET circuits are based on the Mu amp design.

Just another path for the OP to follow.

[Transmogrifox]

After you get done reading the material midwayfair suggested, then the next step gets a little more complicated when looking at an RC  network in the source of an amplification device (BJT, FET, Triode, etc), in this case a JFET.

Because of the way the JFET works, there is a relatively low impedance looking into the source that can't be ignored in the RC calculations because it is typically as low or lower than the source resistor.

This calc can help if you sort of shoe-horn it into the needed parameters:
http://www.guitarscience.net/calcs/cd.htm

For example, with the bias conditions you would be using:
VDD=4.5V
Idss = 0.005
Vp=-2
Vs = 0
RG = whatever you want (ignore input impedance calculation because it will be meaningless)
rd = 820 (from schematic first stage for the 18 you linked above)

This calculator comes up with an Ro = 189 ohms, which is quite a bit different than if you used only the source resistor in the RC cut-off frequency calc.

Even worse, because JFETs vary so much, this can be all over the place with different devices.  You pretty much have to tweak it by ear and then call it "good enough for rock 'n' roll".

As long as you understand that the output impedance of most of these stages will be in the 200 ohm area and that a smaller value of C makes the cut-off frequency higher and that really large (like 10 uF) values will tend more toward a wide-band bypass then you know which direction to go to get the sound you want.

[midwayfair]

After you get done reading the material midwayfair suggested, then the next step gets a little more complicated when looking at an RC  network in the source of an amplification device (BJT, FET, Triode, etc), in this case a JFET.

Because of the way the JFET works, there is a relatively low impedance looking into the source that can't be ignored in the RC calculations because it is typically as low or lower than the source resistor.

This calc can help if you sort of shoe-horn it into the needed parameters:
http://www.guitarscience.net/calcs/cd.htm

For example, with the bias conditions you would be using:
VDD=4.5V
Idss = 0.005
Vp=-2
Vs = 0
RG = whatever you want (ignore input impedance calculation because it will be meaningless)
rd = 820 (from schematic first stage for the 18 you linked above)

This calculator comes up with an Ro = 189 ohms, which is quite a bit different than if you used only the source resistor in the RC cut-off frequency calc.

Even worse, because JFETs vary so much, this can be all over the place with different devices.  You pretty much have to tweak it by ear and then call it "good enough for rock 'n' roll".

As long as you understand that the output impedance of most of these stages will be in the 200 ohm area and that a smaller value of C makes the cut-off frequency higher and that really large (like 10 uF) values will tend more toward a wide-band bypass then you know which direction to go to get the sound you want.

But the 18 is all drain followers, so this calculator doesn't help much. Each stage's output impedance is roughly the value of the drain resistor in that case. So the cutoff calculations vary with the biasing, unless the trim is on the source instead of the drain. I'm not convinced you'd really need to fuss about a couple hundred ohms after a source follower since most tone controls in guitar pedals are dealing with a minimum of a couple KOhms.

[Transmogrifox]

Sorry Jon, but that is incorrect.  The reason I suggested a little bit of abuse of a source follower model is because this principle is at play whenever you have a resistor in the source.  The fact that there is a resistor in the drain doesn't change how the transconductance effects the apparent impedance at the source.  The capacitor in the source sees this impedance, and this is where you will get a different 3dB cutoff than you would expect if using only the value of the source resistor.

Here is a Spice sim to drive home my point:



This happens to agree pretty closely with my suggested abuse of that calculator I linked.   

This is not the same thing as you commonly see referenced as "Ro" with certain small signal JFET models.  This Rs' that I'm talking about is more apparent with other small signal models which use a transconductance-dependent voltage source, where Rs' is the Thevenin equivalent resistor that shows up in series with the voltage source driving the JFET source.  Then the output voltage or Norton equivalent output current is dependent upon the voltage across Rs'.  These models can also include the "Ro" value across Drain-Source which is often neglected because if its relatively negligible effect on the final output gain.

The value of the output impedance looking into the source is rs'=1/gm.  The term "gm" is transconductance of the amplifier.  The online calculator I linked does this based on values you put into it, then calculates rs'||Rs to give you a final value for impedance looking into the source which zips this all up into one value that is seen by the capacitor.

[midwayfair]

Sorry Jon, but that is incorrect.  The reason I suggested a little bit of abuse of a source follower model is because this principle is at play whenever you have a resistor in the source.  The fact that there is a resistor in the drain doesn't change how the transconductance effects the apparent impedance at the source.  The capacitor in the source sees this impedance, and this is where you will get a different 3dB cutoff than you would expect if using only the value of the source resistor.

Here is a Spice sim to drive home my point:



This happens to agree pretty closely with my suggested abuse of that calculator I linked.   

This is not the same thing as you commonly see referenced as "Ro" with certain small signal JFET models.  This Rs' that I'm talking about is more apparent with other small signal models which use a transconductance-dependent voltage source, where Rs' is the Thevenin equivalent resistor that shows up in series with the voltage source driving the JFET source.  Then the output voltage or Norton equivalent output current is dependent upon the voltage across Rs'.  These models can also include the "Ro" value across Drain-Source which is often neglected because if its relatively negligible effect on the final output gain.

The value of the output impedance looking into the source is rs'=1/gm.  The term "gm" is transconductance of the amplifier.  The online calculator I linked does this based on values you put into it, then calculates rs'||Rs to give you a final value for impedance looking into the source which zips this all up into one value that is seen by the capacitor.

Your spice model is a source follower. What does this have to do with the output impedance of a DRAIN follower? A source follower is not a voltage amplifier like what's used in distortion pedals.

[Transmogrifox]

I think the misunderstanding is I'm talking about the high-pass shelving effect by a capacitor placed in the source of an amplifier stage.  I think you (Jon) are thinking about RC time constants for stages following the drain.  This is entirely different, and I agree looking back at the drain you can pretty much treat it what you see is what you get because the drain looks like a very high impedance.

It doesn't matter how it is configured.  The transconductance of the FET under the given bias conditions defines the impedance seen looking into the source.  The capacitor in the source sees THAT impedance, and that is what defines f3dB for that stage.  To clarify, this is unrelated to other RC relationships connected to the drain.

Technically what I showed in sim is an amplifier driven at the source -- to demonstrate the impedance seen looking into the source.  That is just to demonstrate that impedance looking into the source is not what meets the eye, regardless of whether you have a drain resistor hanging on the other end. 

To be more pedantic, here is a sim that shows what this means in a typical JFET gain stage used in a distortion pedal:

Here is the result:


Now if we use a naive assumption that the 3dB cut-off is set only by the drain resistor we have:
f3dB = 1/(2*pi*820*2.2u) = 88.22 Hz

If we consider the impedance looking into the source is not what meets the eye, we have Ro = 189 ohms from online calculator I referenced:
f3dB = 1/(2*pi*177.17*2.2u) = 382.8 Hz

This is awfully close to what the simulation suggests is the 3dB cutoff as seen at the drain.  You get a high-pass shelving effect where the min gain is approximately Rdrain/(Rsource+Rs'), and the max gain is approximatley Rdrain/Rs'.  The 3dB cutoff on this high-pass filter is 1/(2*pi*(Rsource||Rs')*C)

Is it clear now?

[midwayfair]

I think the misunderstanding is I'm talking about the high-pass shelving effect by a capacitor placed in the source of an amplifier stage.  I think you (Jon) are thinking about RC time constants for stages following the drain.

Yeah, I realized on the way home that we were talking about different things ... especially because I forgot that the older ROG designs all had the source cap. Sorry about the confusion and making you type out more stuff.

[Transmogrifox]

Sorry about the confusion and making you type out more stuff.

If it clarified for you, maybe it clarified what I was talking about it for the OP.

nguitar -- now you have some good info about what a cap in the source does to the frequency response of the JFET stage.  You can use it to make a high-shelf filter, which is nice for tightening up the sound without sacrificing too much of the low end.

[PRR]

> impedance of a DRAIN follower?

Not even sure what that is.

The drain does not "follow", it *inverts*.

I have seen unity-gain plate "followers" proposed and analyzed. External NFB resistors set the gain. Under some conditions this can give slightly better performance than the same device as a cathode follower. Often you do not need the "follower" part, you can accept an inverter which is otherwise similar to a "cathode follower".

But a key point in either case is low distortion. Which is outside the OP's interest.

I think it might be clearer to say "common source amplifier".

I hate that name, because it does not say the important parts (where the in and out go). However "Gate-Input Drain-Output Amplifier" is too much of a mouthful.
_________________________________________________________

> What is the purpose of the cap and resistor between the source and he ground?

We need "some" voltage-drop (resistor is cheap and semi-self-balancing) at the Source for DC bias.

We do NOT want extra resistance here because it reduces gain.

The R-C is 820 Ohms for DC and very-low frequency, less than 820 by 4Hz, near 82 Ohms at 43Hz, and "nothing" by the time we get the guitar low-note near 82Hz. This is not tone-shaping. It gives full gain for ALL guitar tones.

> What is the purpose of the cap and resistor between each gain stage?

We want to end-up with +5V DC voltage at the source, zero V DC at the next gate. The resistors pull up or down appropriately, and the cap couples audio signal from one to the next while holding the DC voltages.

[ashcat_lt]

I hate that name, because it does not say the important parts (where the in and out go). However "Gate-Input Drain-Output Amplifier" is too much of a mouthful.

I agree, and really like the way you put that.

The R-C is 820 Ohms for DC and very-low frequency, less than 820 by 4Hz, near 82 Ohms at 43Hz, and "nothing" by the time we get the guitar low-note near 82Hz. This is not tone-shaping. It gives full gain for ALL guitar tones.

This seems to contradict the sim above and about everything Transmogrifix has said.  I personally don't see where the other end of Rs' hits ground (in order to be parallel to RS) except through the RD, which is just shy of that 10:1 ratio where we can completely ignore it, but not nearly small enough to make as much difference as the sim shows.  Is the Drain itself basically ground in this case?

[midwayfair]

I also don't like common source amplifier because it makes it sound like the signal is coming from the source. I remember being very confused about that term. We already use "high pass" and "low pass" which are easy to mix up because they mean the opposite of what the first word implies.

Op, I feel it would be remiss not to thoroughly absorb the Fetzer Valve article:
http://www.runoffgroove.com/fetzervalve.html

I know you're already looking at ROG, but that article contains a lot of information that I think is newer than the 18 design and a ton of little tiny details that explain the choices that can be made for the values on the amplifiers. Some of it might be overly fussy -- I don't personally hear a difference between a FET trimmed to 2/3 supply on the drain with the "magic" values and one tuned to 2/3 supply with other values, so I don't see much value in measuring devices individually, but the article's a valuable resource.

[PRR]

> where the other end of Rs' hits ground (in order to be parallel to RS)

Relative to Gate.

Idealized Universal Amplifying Device (tube, BJT, FET)--



The bottom of the infinite transconductance is a zero-Ohm replica of our input signal.

The total resistance from the imaginary infinite transconductance to common is the bottom of the voltage gain formula.

This is the resistor we nailed into the circuit, plus whatever non-infinite conductance is inside our non-infinite device.

For most small-signal cases, the internal resistance is "similar" (same order of magnitude) to the DC bias resistor, perhaps on the low side of equality. (BJTs require more detail; we often hold the Base much higher than simple bias demands.)

A 12AX7 tube with 1.5K DC bias will be near the 1,600 uMho area or 625 Ohms internal resistance.

I would suspect the common JFET with 820 Ohm bias will give like 400-600 Ohms internal Source resistance.

In both cases, if you look on the Datasheet, be sure to find or correct for the actual operating point. Datasheets often cite a "hot" condition where Gm is highest. We often run well under that point.

[Transmogrifox]

The R-C is 820 Ohms for DC and very-low frequency, less than 820 by 4Hz, near 82 Ohms at 43Hz, and "nothing" by the time we get the guitar low-note near 82Hz. This is not tone-shaping. It gives full gain for ALL guitar tones.

This seems to contradict the sim above and about everything Transmogrifix has said. 

PRR is correct, and he is not contradicting my sim because we're referencing different circuits.  Notice I changed the capacitor value to show the high-pass shelving effect.   In the particular schematic PRR is referencing the capacitor is being used to increase gain at all useful guitar frequencies.

My post was in response to the following question:

As you can see the top "treble" gain stage have a 2.7k/680n couple while the bottom "normal" gain stage have a 820r/330uf couple. How those values is calculated/determined ?

In that post I am assuming he was referring to R6 and C6, which are in the source of the JFET.  Now I kind of went nonconventional to demonstrate the concept where I changed the 330uF to 2.2uF just to demonstrate how the source impedance interacts.

With a 2.7k, the source impedance will be higher because bias current is lower, which means less transconductance.  If the OP uses the online calculator I posted with the suggested typical FET values, he can figure out where the 3dB cut-off on this particular treble boost stage is located.

Jon (Midwayfair) posted some good links for understanding the concept of RC time constants and how to determine these from most places in the circuit.

I pointed out the "gotcha" with impedance looking into the JFET source not being WYSIWYG.

PRR (above) pointed out a rule of thumb that gets you close.  He states with a 820R in the source he would expect internal R to be of the same order of 800 ohms, with a parallel combination of around 400 ohms.  Even though this is double what simulation and gm calculation suggest, it isn't really that bad of an approximation considering how much JFETs vary within a lot, and from part to part.  It's good enough to get some components stuck onto a breadboard.  If you know the general relationship then you know what to do with those components to make it sound the way you like.

SPICE is nice, but the sim can't be trusted to give you something representative with the real circuit when considering real variability in part tolerance.  You can do a Monte Carlo sim in SPICE to see several traces with a weighted random combination of component tolerances, but this still doesn't tell you whether the design sounds good to begin with.

Whether using SPICE or "back of the envelope" calculations, you still need to play around with components on the breadboard to get your sound, then you transfer that to the PCB or other permanent implementation and go with that.