plz kindly help me bias a jfet

[ehsan_zt]

Hello DIYers,

I know you are probably bored by "jfet biasing" topics... I've gathered as much information as I could on this topic, read various guides, but I'm still facing some problems. Unfortunately I'm not fluent neither in English nor Electronics which adds to the confusion, but I'm not giving up on this. If someone would be kind enough to answer some questions, I think I will FINALLY get it.I know the basics and "logic"s and "why"s behind biasing, but I have some problems in calculating resistor values.
The only JFET I can get are 2n3819 which has Vp of around -3 and Idss of around 10mA. I'm looking to bias each jfet for maximum voltage gain without clipping and I don't want the quick easy solution which works for many jfets,I want proper and optimal way which involves numbers and formulas (because I need to change every circuit which uses jfets so that it can work properly with 2n3819).here are some questions :

1- when we want to set Rs(source resistor) do we shoot for Vgs=Vp/2 or Id=Idss/2 ?
2- if the answer to question 1 is Id=Idss/2 then how do we measure Vgs of that Id ?
3- how do we calculate Rd(drain resistor) to provide a voltage half the power supply? is there a formula?
4- we  normally set the source resistor, then we set the drain resistor, but after setting the drain to half of power supply , Vgs is not at the voltage we picked first , is that OK ?
5- I know power supply voltage restricts maximum gain, is there a relation between "proper" power supply voltage and Vp ? for example 9v is enough for Vp=0.5 , but not for Vp=4 ...

I have some other questions, depending on answers to above question I will ask them later. Thank you for your time and patience. 

[smallbearelec]

Hi--

I selected the source resistor to put the drain current at 1/2 IDss, then set the drain resistor to put the drain voltage at about 1/2 the supply. This article:

http://diy.smallbearelec.com/HowTos/BreadboardBareAss/BreadboardBareAss.htm

goes into detail.

Regards
SD

[ehsan_zt]

Actually I've read your article and it helped me ALOT with biasing, but it doesn't answer all above questions. I'm looking for formulas so that I can have a point of reference when I'm trimming source and drain.

[PRR]

If you want HIGH gain....

Figure out the LOAD which the stage must drive.

Pick the Drain resistor 2 to 5 times smaller.

Check: Supply voltage divided by Drain resistor must be less than Idss. (Probably not a problem for 2N3819 in most small audio circuits.)

Use a variable resistor to find a Source resistor which sets the Drain a little higher than half of the supply voltage.

To be very conservative: stack-up Vp twice, aim the Drain to the middle of what is left. So for Vsupply=9V, Vp=2.7V, you figure 2.7V+2.7V=5.4V, there is 3.6V left to reach 9V, half of that is 1.8V, so Drain should be near 7.2V. (Which is why you do NOT want Vp=3V devices in a 9V world!)

You will want to bypass the Source resistor. 10uFd for "full guitar", 100uFd for High Fidelity, 1uFd or less for "bass-cut guitar".

> Id=Idss/2 ?

For good gain you want the *lowest* current which will drive the load, not half the maximum.

> Id=Idss/2 then how do we measure Vgs of that Id ?

We do not want that point, but: probably 0.6 times Vp. (Square Law.) Not Vgs=Vp/2.

> a relation between “proper” power supply voltage and Vp ?

Power supply voltage should be much more than Vp. 10X would be nice. With '3819 at 9V you only have 3X.

[ehsan_zt]

Thanks for answering.
This method is different from what smallbear used in his article  is this the "rule of thumb " kind of biasing ?

- Figure out the LOAD which the stage must drive.
how can I measure load ? I'll be connecting this jfet stage to a one transistor distortion.

- To be very conservative: stack-up Vp twice...
but if I set the drain to be exactly half of power supply, it will sounds louder or at least in my setup it does.

- For good gain you want the *lowest* current which will drive the load, not half the maximum.
I thought we should set the Id to half of Idss because it gives room for our signal to bounce up and down ,or were we supposed to do that for Vp?

I should mention that I'm using first 3 circuits of "biasing jfets" by smallbear to measure Vp and Idss,and creating that table of Vgs and Id, after that I'm using these formulas to figure out resistor values:
Id=Idss/2 (from table I have Vgs of this Id)
Rs=Vgs/Id
Rd= (Vcc/2)/Id
, but according to what you said these are wrong