Correct biasing of 2N5457 Booster-Buffer circuit

[iefes]

Hey folks,

I read a lot about how to determine suitable resistor-values on a JFET Boost circuit from reading articles over at runoffgroove and amz etc.
I want to build something like the Baby Pink Booster from BJFE but with a 2N5457. I breadboarded it and got some nice results straight away with the resistor values from the original 2N5952 layout.
However, I determined Idss and Vp with the method suggested by ROG (got Idss: 2.97mA ; Vp: 1.43V). Using these values the calculator gave me a drain voltage of around 6.4V, corellating to Rd = 1860 Ohms and Rs = 400 Ohms.
Now, am I right that these values are those I should use if I want the boosted signal? If yes, why do circuits like the EP Booster have higher values for these resistors (8k2 and 4k7)?

To get a signal around unity gain I used resistor values like in the schematic attached (8k2 and 5k6) with the wiper of the gain-pot not connected to ground. In this setup I get a Drain voltage of around 7.6V. Is this how it should be? When connecting the wiper to ground and turning the knob CW I get a quite good boost, but not as much as I would expect from a Boost-pedal.

So my questions are:
- How do I know which values for Rd and Rs are best to achieve unity gain in one mode and a Booster when the pot-wiper connects to ground?
- Should Vd be around 6.4V even when I want to achieve unity gain or can I only have unity gain when running on higher Vd? (like I am doing at the moment)
- How can I calculate the maximum gain of this circuit? (Av = 0.5 * (Rd/Rs) ? )
- How could a higher Boost-potential be achieved without adding a second stage?

Thanks a lot!

The circuit my breadboard circuit is based on can be found here: http://revolutiondeux.blogspot.de/2013/03/bearfoot-bjf-baby-pink-booster.html


Edit: Sorry, but I couldn't figure out how to add an attachment. The "Attachments and other options" button doesn't give me this feature.

[PRR]

Welcome!

To get unity gain with that circuit, start with Rd=Rs, then make Rs a little smaller to account for the internal resistance inside the FET. I'm not sure that asking for both unity-gain and boost in the same circuit is best design. You could just bypass it with a switch to get unity gain, then optimize the boost to boost.

To get maximum voltage gain, bypass Rs completely and make Rd about 1/2 of the external load resistance (which we often do not know exactly). For most guitar-cord loads, this leads to Rd (and Rs) in the area of 25K-50K. However then small changes loading make major change from "unity" gain in no-boost mode.

The drain voltage will be what it will be. The circuit you have picked does not offer any choice in the drain voltage you get. It will depend on JET parameters. Since Rd must be nearly equal to Rs, and Rs will drop whatever voltage the FET gate-source action wants, Vd will be about the same amount down from battery voltage.

It's all compromise. More parts lets you isolate compromise trade-offs for optimization. Two FETs and a switch, you can make a unity-gain bufferm +and+ a boost-only booster. One opamp (40 parts inside a chip, but fewer parts in your build) can do unity-gain and "any" desired boost.

[iefes]

Thanks a lot for your reply! This makes things a little more clear to me.
But I have some questions remaining:

What do you mean by the suggestions to bypass "it" with a switch and then optimise the boost to boost? Do you mean I should bypass the whole buffer-stage and have another stage which will just function as a boost on its own? Yea, I was thinking about something like this but would love to keep the parts kind of low like in the original example.

If I get you right, I shouldn't worry about the drain-voltage in unity gain mode and just adjust it to taste?

How do I know in which range of resistor-values I should start for Rd and Rs? I saw some design in the range between 3k and 15k but does it matter? Are there cases where it matters eg. Buffer compared to Boost?

So, I'm realising that I am dealing with compromises but I liked the sound in the first place so I think I will go on trying with this one.

Could you give me advice on how to calculate the gain of the circuit? If I use the equation posted before I get a boost of around -2dB but as I clearly gets louder, so this doesn't seem to make sense to me...?

Thanks a lot!

[antonis]

I think that Paul suggested to bypass the Source resistor by "short-circuit"..
(Source straight connected to GND or whatever voltage is on the lower side of Rs - just like BJT without Emitter degeneration)

This action results in getting "maximum" gain from the Drain (depending oh Rd value).

With both Drain & Source resistors the Voltage gain is roughly Rd/Rs which leads to get equal resistor values for buffer purposes (Vout from Source) or phase reversed unity gain (Vout from Drain).

Paul said for a small resistor difference to compensate for FET's internal resistance (between Rd & Rs).


P.S.
Resistor values for FETs aren't so "strictly" calculated as for BJTs...

[midwayfair]

Let's put the schematic a bit more visible for everyone giving advice.



There are two "bypasses" going on here. One is the bypass of the effect. The other is the one PRR was talking about, which is "bypassing" the source resistor with a capacitor.

The source on the Baby Pink Booster is bypassed by a large capacitor by an amount set by the boost pot when the "bypass" switch isn't disconnecting it. The DC bias is fixed.

The maximum boost is R5/R6 NOT R5/R3 -- R6 is a 1K blocking resistor for the capacitor bypassing the source (C4). When you've disconnected the boost pot, you've got 150K blocking that capacitor, which is >10x bigger than the source resistor and now the capacitor has "no effect."

The source and drain values were chosen here to give roughly unity volume when the capacitor is no longer allowed to bypass the source resistor.

Runoff Groove's stuff isn't really relevant in this case. They're providing information on the boosting capabilities when no source bypass capacitor is used at all (where the gain will be Rd/Rs).

The drain voltage is also pretty much irrelevant. It doesn't affect the amount of boost you get. It does affect the distortion if you clip. The 2N5457's Vp will also limit how big the input signal can be.

You should get over 22dB of boost with this circuit. It's hard to imagine that's not enough for most peoples' purposes. If you want more you can reduce or simply short R6, but there's going to be a limit to what you can squeeze out of any given FET.

There are some things that strike me as weird with this circuit. I'm not sure why the higher values were chosen for the drain and source resistors, because these make the receiving circuit's input impedance more important (lower = more loss), are much larger than they need to be for this FET, and the 50K pot won't really have a great feel, since it puts +6dB at noon ... that's a lot of travel for such a small amount of boost. I would sooner cut the drain and source resistors by half, make R5 220R, and simply use a 5KC for the gain pot.

[iefes]

Jon! Thank you very much. This really helped me a lot. The fact that the gain is determined by R5/R6 really helps me understanding the whole thing.

I will try some of your suggestions and sort out a setup that suits me. So if I get you right, the effect of the bypass (---> Boost!) gets larger as the resistance between GND and C4 decreases. Could I consider Rs is R3 parallel to R6 and the Boost-Pot? This would yield a resistance of Rs = 0.9k when fully cranked (12k parallel 1k) or a resistance of Rs = 9.7k when fully ccw.

However, this is a good starting point for me to work with :-)

[PRR]

> I shouldn't worry about the drain-voltage in unity gain mode and just adjust it to taste?

You can't even adjust it (much).

For unity gain, Rd is nearly = to Rs. (Rs will be about 1K smaller for unity gain.)

I(Rd) == I(Rs).

Therefore V(Rd) == V(Rs).

V(Rs) is, in this circuit, controlled only by FET properties. And for practical current, will change very little with reasonable change of Rs (and Rd).

Therefore V(d) is essentially 9V minus V(Rs), and not independently adjustable.

[iefes]

Much to learn for me even on such a simple circuit :-) Thank you all!

[Gargaman]

I'd like to thanks for this thread too! Very usefull to me in this moment.
I'm gonna keep reading untill drain all the information.
Let me share one observation: can I say that, in generic words, if you take a JFET (2N5457), common source config and your output is taken from the source, then it's a buffer (AMZ Jfet buffer/ruby amp input buffer)?
If you take your output from the drain, then it's a booster? (Fetzer Valve / other Jfet booster)

[iefes]

Hey Guerrilha, I don't think that's right. As far as I understand Jack Ormans article on AMZ, the signal taken from the drain is inverted whereas the signal taken from the source isn't inverted.  Whether it works as a Boost or Buffer is determined by the values of Rs and Rd. :-) right?

I tested that little circuit a little more and drew up a schematic of the circuit I came up with. See below. This works like a charm and adds some nice sparkle because of the high input impedance.

I tried to implement the SWTC as a LPF on the output to have the possibility to roll off some highs if it gets too sparkly but it didn't work out. I tried a lot of different resistor, trim and cap values but I never managed to have the "unaffected" (for humans ears) sparkly signal even when the trimpot was completely "open". When I tried very low values for the first resistor (33R) and the cap (3n9), it was very sparkly but the 10k trimpot wouldn't allow a noticeable sparkle roll-off. Hope that was understandable.
If you have a suggestion how to implement a simple presence roll-off with the opportunity to keep the presence completely alive, feel free to share :-)

Thanks a lot!

[Gargaman]

Hey Guerrilha, I don't think that's right. As far as I understand Jack Ormans article on AMZ, the signal taken from the drain is inverted whereas the signal taken from the source isn't inverted.  Whether it works as a Boost or Buffer is determined by the values of Rs and Rd. :-) right?

I bet you are. I'm learning here. I'm trying to compare applications of the JFET (here I use 2N5457) in those building blocks that I quoted in attempt to understand the bias process, how to get unity gain, etc.
Again, I'll be reading the thread for a while.
Sorry if I miss the focus a little bit.
regards

[iefes]

No worries, two days ago I wouldn't have had any clue at all

[Gargaman]

So, you learn fast bro!

[duck_arse]

iefes - I think your input cap at 1uF is at least 10x too big, with those 10M resistors. you might get blocking distortion, and no-one wants that.

[iefes]

I see, I will try small values. Should I just have a look at the cutoff frequency of the HPF it forms with the 10M to determine which cap is big enough?

[ashcat_lt]

OK guys.  This thread has kinda got me freaking out.  Maybe I should make my own thread, but I'm hoping one of you can maybe just talk me down a little.

So, like, the whole action of the transistors depends on the voltage relationship between the gate and the source.  You can call it current if you want, but ultimately all that matters (in a N-channel JFET like this) is how much more positive the source is than the gate.  The gate idles at 0V, and the whole point of the source resistor is to make the voltage at the source more positive than that.  Fine.  Good.

Now what's freaking me out is that the voltage at the source moves!  Grain goes down, Source goes down more (if we've set it up for gain), and so how do we ever calculate exactly what that Source voltage is going to be?  When I start trying to figure it out I end up in some MCEsher painting or like one of those Black Sabbath video feedback things. 

WTF?

[Groovenut]

IMO, just calculate it at idle with no signal input and let the chips fall where they may 

[ashcat_lt]

IMO, just calculate it at idle with no signal input and let the chips fall where they may 

Don't we still have the same problem though?

[Groovenut]

If you know the internal resistance of the fet, you can use ohms law to calculate the voltage drop across it. The same is true for the source and drain resistors. So now the fet amplifier stage looks like 3 resistors dropping voltage across each as the string goes to ground.

[PRR]

> in generic words, if you take a JFET.., common source config and your output is taken from the source, then it's a buffer.... If you take your output from the drain, then it's a booster?

You can extend and correct that.

All the useful amplifying devices, Tube BJT or FET, work the same. For almost all audio purposes we put signal in at the grid/base/gate. We can get signal out at cathode/emitter/source, but the voltage gain is a little less than unity. We can get signal out at plate/collector/drain and maybe get voltage gain (depends on device and resistor parameters).

One example is the split-load phase inverter, "Cathodyne". It has two outputs, at plate/collector/drain and at cathode/emitter/source. We pick equal resistors in each end. Both are voltage gain of ~~0.95. As iefes has said, one is inverted and the other is not. In audio, "usually" we do not care about inversion. But sometimes we care, and sometimes we need it.