Correct biasing of 2N5457 Booster-Buffer circuit

[iefes]

Thanks once more jon!

I put my circuit on the breadboard again and biased the gate of the fet through a 10M resistor to Vr, which is provided by a voltage divider made by a 50k trim pot. This helped a lot but when the gain pot is fully cranked it's still distorting with the high output pickups of my friends guitar. This time I used a J201 as I read this one should have "more headroom". I will also try other JFETs to find one which provides the most clean headroom.
I also ran this thing on 18V. This wouldn't help with distortion but made the whole thing a bit louder.
I think I will increase the gain-limiting resistor between the bypass cap and the gain pot (470R atm) and increase it a bit. Hopefully this won't reduce the maximum gain too much.

If you have other sugestions what I could try, I'd be happy to read about it. Or suggestions for other JFETs which might be a good choice in this application are also appreciated.

Thanks!

[midwayfair]

This time I used a J201 as I read this one should have "more headroom".

Exactly the opposite. Who told you that?

JFETs have an inverse relationship between the amount of gain they will provide when biased a certain way with drain and source resistors and how much headroom they have at the gate. Read Runoff Groove's FETzer article for a pretty thorough explanation. There's a number in the datasheet that can give you some clues as to how a FET will behave, but the short version is that if you grab a J201, you could probably bias it to 9V with, say, 18K on the drain and 1K on the source, which is 18x gain, while a 2n5457 would probably only need 10K on the drain resulting in 10x gain. But the 2N5457 would be able to take a larger signal at its gate, never mind whether 18x vs. 10x clips the power rails of the circuit. It's a device-level issue.

If you increase the supply voltage, you'll not only be able to squeeze more gain out of them, but you'll be able to get a bigger signal at the output because the signal won't clip the power rails as readily. Now you're more likely to clip the next device in line, whether it's another FET or your amp. A 12AX7 in a typical amp can only take about 2.25V p-p on its grid before it distorts -- a booster boosting humbuckers can easily hit that.

If you need more headroom, you either need to look at lower-gain FETs like the 2N3819 or 2N5459 (there are plenty of others and you'll have to load up a lot of datasheets), which probably won't let you get much boost, or abandon the idea of using a FET for a clean boost.

[iefes]

Okay! Thanks again! I was reading some other topics and probably got confused by all the different JFET properties.

Well, so it looks like I have to find a compromise which suits my needs or try a completely different approach. I think I will try different transistors and read the article over at runoffgroove (as I already started) and try other stuff.

What I am still wondering is whether it is better to bias the gate with respect to Vr or to GND. I am using a trimpot on the breadboard to provide Vr but I can't really hear a difference (distortion-wise) when biased with respect to GND.
Can you clarify this for me? In the Fetzer valve article there isn't any information about biasing with respect to Vr.

Thanks for this great support!

[midwayfair]

What I am still wondering is whether it is better to bias the gate with respect to Vr or to GND. I am using a trimpot on the breadboard to provide Vr but I can't really hear a difference (distortion-wise) when biased with respect to GND.
Can you clarify this for me? In the Fetzer valve article there isn't any information about biasing with respect to Vr.

Ground is always 0V. It's never anything else and it should never make any noise to pollute the audio. It also involves only one resistor. It's useful when you're prioritizing low parts count and low noise.

Gate biasing requires a voltage divider for the reference voltage (usually a trim, which is many times the cost of a single resistor) and a likely a large capacitor to filter the Vref. It's useful when you're prioritizing exact gain multipliers using the drain and source resistor ratio, or if you've fully bypassed the source and want to tailor the symmetry of the waveform. It's also useful if you want to make a design that can accept a BJT instead of a FET (which is when I use it -- in mic preamps) or even a MOSFET, which is an excellent device for making boosters with high input impedance and headroom, by the way.

One thing you likely won't run into is that there is a maximum voltage difference a FET should be exposed to between the source and gate. It varies from device to device and you're probably have to work hard to get it working in a way that would risk damage.

[PRR]

> maximum voltage difference ...between the source and gate. It varies from device to device

It is un-likely to be anything other than a "36V" process, though for JFET Gates they usually give 20V as the limit. To cover incidental production slop, and because high voltage spoils the JFET's best feature (high input impedance) with leakage. You would *never* want 20+V G-S. Typically just a few V or less.