Op-amp bias problem

[Rixen]

IMHO, you should place a DC blocking cap between IC's out and BJT's base, bias independently BJT and place a current limiting resistor (just in case..) on IC's out...

+++++ for Vref capacitor...
(try to place an IC voltage follower on Vref with a capacitor on it's out to see if Vref is well stabilized..)

the transistor is connected as a voltage follower, so the emitter voltage will be 0.6v lower than the op amp output, and no voltage gain- no real need to block dc in this case and the impedence seen by the op amp output will be the emitter load x Hfe, ie: quite a high value that won't overload the op-amp 

[TejfolvonDanone]

After everything i tried nothing really helped. I swapped out the IC to a TL071. The bias got better and only going to 1.5V (minimum output for the op-amp) at around 70k of the pot. I also inserted an offset compansating trimmer (as the datasheet suggests) but the only thing it has done was to rise the output to 7.9V with no adjusting available.
Also inserted a cap between Vref and ground. It obviously didn't help with biasing.

no, place it between the inverting input and R1- so that both inputs see ~500k 

It didn't really do any good. The op-amp gone into a really bad oscillation. Also added a resistor between non-inverting input and R7 as the common bias current compensating technique only to make the whole situation worse.

(try to place an IC voltage follower on Vref with a capacitor on it's out to see if Vref is well stabilized..)

I know that the bias voltage isn't stable and i don't really mind if it drifts a few mV unless it goes under 3.5V. (The minimum output for the op-amp + 2V for the soon-to-be-added Zener)
Adding another op-amp would be really problematic for my current build.

[TejfolvonDanone]

As my last attepmt to resolve the issue i asked my boss to help me. The solution was interesting for me yet wonderful. So we cut the connection between the op-amp output and the pot and connected the pot directly to the emitter of the output buffer. Now everything works super well. The output now sits well at the Vref doesn't move from it if i turn the pot. I'll post an updated schem when i get home so everybody can see it.

[antonis]

the transistor is connected as a voltage follower, so the emitter voltage will be 0.6v lower than the op amp output, and no voltage gain- no real need to block dc in this case and the impedence seen by the op amp output will be the emitter load x Hfe, ie: quite a high value that won't overload the op-amp 

Maybe you didn't nοtice my <just in case..> comment..
(which would be a 3R9 resistor instead of 3k9 one..)

P.S.
Your theory for need of blocking DC ONLY in case of voltage gain is quite interesting..
(I was always thinking of upseting bias only at signal's swinging range is advisable despite of voltage gain, equality or attenuation..)
After all, a voltage follower is an amplifier with gain slightly less than unity..)

[antonis]

Τhe solution was interesting for me yet wonderful. So we cut the connection between the op-amp output and the pot and connected the pot directly to the emitter of the output buffer.

Placing emitter follower inside the closed-loop it's a kind of "old trick" used for Vbe drop compensation & bias instability issues..

[TejfolvonDanone]

...it's a kind of "old trick" ...

...and yet nobody mentioned...

[antonis]

...and yet nobody mentioned...

That's because of trying to prevent you from the trouble to compensate for the raised feedback gain... 
(β times Emitter resistor is added in series with the gain pot..)

[TejfolvonDanone]

This is the final build which works as i intended. http://www.aronnelson.com/DIYFiles/up/Z_DIST.pdf

[TejfolvonDanone]

That's because of trying to prevent you from the trouble to compensate for the raised feedback gain... 
(β times Emitter resistor is added in series with the gain pot..)

Actually i just used one transistor not a complete emitter follower. So it doesn't increase the gain that much.