cd4049UB consistency problem?

[dschwartz]

hi there!
i´m trying to add a gate control to a red-llama style gain stages..

there are 2 inverters in series , one with 22X gain (10k/220k) and the other with 4x gain (100k/470k)

i noticed that when placing a 1M R to ground at the input of the first inverter, there was a gating effect, so i added a bias pot that varies the 1M potential between 1/2 Vcc and GND..very similar to the gate control on the "insanity box" design

the thing is.. i built one, and worked perfectly, i can adjust the gate treshold with the pot and eliminate hiss and feedback nicely (not a decimator, but it gets the job done)

then, i built another one..exact same parts, almost the same layout (the first one was a frankestein style flying wires to experiment).. but it doesn´t gate at all..just changes the bias without cutting the signal down completely as the first one did..

the theory of this gate idea, i think, is to introduce an offset bias on the first inverter, that gets amplified by the second inverter so the signal runs near the rails..as cmos inverters have a nearly flat transfer curve at the extremes of the input range, when a signal is biased high enough, and has little amplitude, it will be transformed into a logical output.

the thing is.. why does it work in one build and not in the other..my hypothesis so far is that the "logic limit" of each chip are different..

i´m limiting the cmos current with a 1k , so the Vcc is around 5 volts..  with the gate full on, i get 0.55mV DC on the output on the one that works.. and 0.7V on the one that doesn´t..

are cd4049´s inconsistent as fets? or did i do something wrong here?

[R.G.]

For an answer, look at the detailed analog characteristics of the CD4049UB datasheet.

Oh, wait! There isn't a section like that!

Yes, they're likely to be inconsistent from wafer to wafer in the same manufacturer's diffusion furnaces, and more inconsistent from different manufacturers and furnaces.

And yes, they *are* FETs inside. 

Analog uses of CMOS are happy side effects, and not likely to be guaranteed by specification. Even if they work for one brand/vintage chips, they may not work for others.

[anotherjim]

You have calibrated weights but different balance scales. They tip differently despite using the same weights. You need to calibrate the scales. Try tweaking feedback resistance (balance) as well as the bias (weight).

You might also have more luck if you use a regulated lower supply instead of a dropper (or maybe just a large C on the Vcc pin) - but it might sound different. Remember the shoot-thru current when P & N Transistors in the inverter are both partly on. As this comes & goes with signal, it will play the voltage drop across the Vcc dropper resistor and all the inverters used in the chip will interact with this, changing conditions you are trying to set.

[Rixen]

There are transfer characteristics for the 4007 showing the tolerance of the operating region (fig 6 on page 3-16), and IMHO the 4049 is likely to be similar to the inverter of the 4007 (which makes a great sounding MOSFET distortion BTW)
http://www.ti.com/lit/ds/symlink/cd4007ub.pdf

these curves do, of course, become less steep with the introduction of negative feedback.

[dschwartz]

Man that sucks...I'm designing for production, so trimmers and hand adjustments are a big no no.

I thought cmos inverters were much more consistent than fets..they sound amazing when properly adjusted.. 
So now back to the drawing board and maybe use the old back to back diodes for gating.. But i have the 4049 at 5v so i'll have to amplify a lot to get a decent gate threshold vs amplitude..

[dschwartz]

Maybe if instead of  lowering the bias towards ground, i lift it up to Vcc and above, so i have more room to play.
Can input voltage be above Vcc?

[anotherjim]

Remember the Si protection diodes on the inputs (even the 4007 has these). Provided there is sufficient series R to limit input current when these diodes conduct, it should be safe to exceed Vcc. I think specs do quote a maximum input current & although it doesn't say so, this must be for the protection diodes?

[Rixen]

..I wonder if it would be possible to use one of the unused inverters, with negative feedback, to provide a reference voltage from which to derive a bias voltage. Being the same piece of silicon should compensate for component tolerance..

[anotherjim]

Yes, you can wire an inverter as a buffered Vref.

Just throwing ideas out there, but if it's gate action you want - you have 2 inverters - DC couple them and put an overall feedback resistor from last out to first in. Add series resistor on input. You than have a Schmitt trigger. Lower input resistor to lower the threshold.

[dschwartz]

The schmitt sounds interesting, but it might just square the signal ..i will simulate to check that out

[R.G.]

Man that sucks...I'm designing for production, so trimmers and hand adjustments are a big no no.

Designing for production is a demanding discipline. If you plan to go into this, never specify anything that you have not personally read and understood the entire datasheet of parts you specify, including especially what is and is not guaranteed for the parts, and crucially, the likely range of variation. Not fully understanding the datasheets may mean that parts which are entirely normal according to the datasheet will not work in your design, or that parts may have to be hand selected for manufacturing. This can be even more costly than doing trimming and adjustment.

Fixing a design defect in the concept phase may cost one unit. Fixing it in the prototyping phase will probably cost 5U to 10U. Fixing it in manufacturing will cost 50-100U. Fixing it once it's shipped can be another 10x to more. You can't fix it in design if you don't know it's wrong.

Not understanding part specs and variation amount to wishful thinking (with all that implies) that your production line will never experience parts variation that's "too bad". We used to call this "you bet your job".

[dschwartz]

Man that sucks...I'm designing for production, so trimmers and hand adjustments are a big no no.

Designing for production is a demanding discipline. If you plan to go into this, never specify anything that you have not personally read and understood the entire datasheet of parts you specify, including especially what is and is not guaranteed for the parts, and crucially, the likely range of variation. Not fully understanding the datasheets may mean that parts which are entirely normal according to the datasheet will not work in your design, or that parts may have to be hand selected for manufacturing. This can be even more costly than doing trimming and adjustment.

Fixing a design defect in the concept phase may cost one unit. Fixing it in the prototyping phase will probably cost 5U to 10U. Fixing it in manufacturing will cost 50-100U. Fixing it once it's shipped can be another 10x to more. You can't fix it in design if you don't know it's wrong.

Not understanding part specs and variation amount to wishful thinking (with all that implies) that your production line will never experience parts variation that's "too bad". We used to call this "you bet your job".

Thanks RG
I'm still in the design phase. I read the datasheets and in figure 1 it shows how the hysteresys voltage may vary between 1v and 4v for 5 v operation.. I though inverters were consistent, but they are consistent inside one chip, not between different chips. So this is a big dissapointment and sends me right back to the protoboard, simulations and layout.

Now i think i know why there are so few cmos distortion models..i have two identical prototypes and they sound very different..both good, but the gain range are different..and the lower gain one is the one which the gate won't work.

I think i will not use cmos and go with opamp implementation..the important thing is filtering over clipping method..

[dschwartz]

Just as an update
I tried using opamps, but i got nowhere near the sound of the cmos inverters. So i ended up with the w2 inverters followed by inline back to back diodes with a pot in parallel to control the "attenuation" .the threshold is fixed but it works ok killing the background hiss on high gain settings. I followed the diodes with an extra inverter with low value input and feedback resistors to attenuate a lot  under the diodes voltages..works great..and much more consistent than trusting the cmos parameters...

[anotherjim]

Diodes are neat solution. You're right about the schmitt trigger idea, I think I was trying to get at using some positive feedback to steer the input, but if gain is so variable, that would probably still need tweaking case by case.

It's hard to pin down the inverter gain close to the rails. I've seen it around x6 to x8 at the point the output can be seen to start limiting on the scope. My thoughts at the moment, if you want the sound of an inverter to be consistent, use an op-amp first for gain. Run the inverter at lower supply so it is always that that's limiting, not the op-amp. Set the inverter gain low - unity if possible, then its gain can never fail to be consistent. If you want the signal to live close to one end of the S curve for maximum asymmetric distortion, offset the op-amp's reference voltage and DC couple the inverter.

[Rixen]

..this is probably a bit late, but I had in mind something similar to this:



the inverter is a 'spare' one in the package, input Voutput-bias is the voltage you want at the output of the inverter you wish to control, Vbias is the bias voltage that you then feed in to that inverter (via a resistor) to fix it's output close to Voutput-bias...

so if you want your crunchy distorted inverter operating 1 volt from the negative rail, put 1 V into Voutput-bias, and feed Vbias (through high value resistor) to input of crunchy distorted inverter... guitar signal will of course need to be AC coupled into crunchy distorted inverter...

..disclaimer- I have not tested this.. it will be dependent on how closely matched the inverters are within the package..

Julian
www.rixenpedals.com

[dschwartz]

Very good ideas indeed!
I'm actually boosting the inverters with an opamp with feedback clipping, my goal was to get that "ts boosted" amp feel.. And it works. I control symmetry, gain and voicing from the opamp stage and the inverters are there for post clipping compression. I also use spare inverters for active eq (i placed the diodes between the post gain inverters and eq section).
The circuit is very low noise until max gain, and the gate is there to control the excessive pickup squeal caused by the inverters compression effect when cranked..but also the noise reduction is a nice thing to have..i found that a 100k pot in parallel with the diodes and a 100n cap to ground lets you dial pretty seamless gating..