General FET question

[sbirkenstock]

Hi Everybody,

just to figure out how things work with FETs I took a 2N7000,
put the source to ground and the drain to 9v with a 10K resistor in between.
Then I applied different voltages to the gate.
At 0 volt at the gate the Mosfet was open (my guess a few ohm over the transistor), and I had 9v at the drain (after the 10k).
Then I increased the voltage at the gate and to my surprise the drain voltage only started changing (going under 9v) when the voltage applied to the gate was at least 1,66 volt.

At 2,11 volt the drain had 4,5v
At 2,5 volt on the gate the voltage at the drain was basically 0. (like 0,005 or so)
At 2,6 volt and higher there was no change in drain voltage any more. Guess that is cut off or pinch off then. At least realtive the the 10K.

I tried it again with a 1K resistor instead of the 10k drain to 9v.
Angain surprise, I needed to apply 1,8v this time that the drain voltage started to go below 9v.

I knew that there is a cut off voltage, but it seems that there is quite a voltage "on the other side" as well, so that the transistor starts having a resistance.
Is there a name for that?
Are my findings "correct", or is there any mistake?

What I was looking for was kind of a "Vgate" resulting in "DS resistance" curve.
So I applied different resistors between Drain and 9V.
Then I dialed in the right gate voltage to half the 9V at the gate.
Here is my little table:
1. Column:  Resistor Drain
2. Column:  Gate Voltage that the drain goes to 4,5V:

1K     -  2,36v
10K    - 2,11v
100K  - 1,92v
1M     - 1,75v
10M   - 1,39v

If the drain is 4,5v = half of the 9v,
then the drain resistor and the resistance of the transistor should match.
I found the gate voltages for the different resistors way too close together.

Guess something in my logic does not work! This does not seem right or be working parameter for a working amp.
Any hint?

Best regards,

Stephan





Best regards,
Stephan

[Rob Strand]

You results look OK to me.  They are measurements - they are what they are.

As for explaining why:  The effect you are seeing is related to changes in the drain current.

In order to get 4.5V on the drain, the current through the drain resistor must be,

  Id = (Vsupply - Vdrain) / Rdrain
      = (9.0 - 4.5) / Rdrain

So as you make Rdrain larger the drain current required to keep Vdrain at 4.5V gets less and less.


Now look at figure 6 from this 2N7000 datasheet,
https://secure.hosting.vt.edu/www.opel.ece.vt.edu/reference/DataSheets/2n7000-03.pdf

The thing to note is as drain current gets smaller the required gate voltage get smaller.
When the gate voltage is around 2.2V it becomes hard to read exact values from
the graph.  However the thing to note is the base of the curve flattens off and you can imagine
at tine currents it will be someone around the 1.39V you see with the 10MEG drain resistor.

For the current used for effect pedals they are operating in this region where the datasheet isn't clear.
However a real device does behave in the way you are seeing.

[If you want you can look-up the theory and equations for a MOSFET and they will show a similar *shape*
curve to the data.   In reality the fine detail of MOSFETs behaviour is quite complex and the equations are only a
simplification.]

Look here also,
http://my.ece.ucsb.edu/York/Bobsclass/2B/Labs/2N7000data.gif

[R.G.]

A crude, but useful model to keep in mind for MOSFETs - not JFETs! - is that there is a threshold voltage for Vgs below which nothing happens. When Vgs reaches that threshold, channel current starts flowing. Additional "enhancement" voltage on Vgs allows more current to flow in the channel. The additional current flowing per additional Vgs is idealized as the transconductance: change in current in the drain per change in voltage on Vgs.

As Rob notes, the actual behavior is quite complicated, so this is just an approximation. But it's been a very useful one to me, and to many in the industry.

In general, good circuit design technique starts with recognizing that many characteristics of active devices cannot be closely controlled or predicted, and then proceeds with techniques to make that which cannot be controlled or predicted irrelevant. Good design makes device variation irrelevant within large ranges by forcing circuit performance to rely on things we can predict - like resistors, capacitors, and inductors.

[PRR]

> drain resistor and the resistance of the transistor

The MOSFET does not really act like a resistor.

In your tests that seems a fair assumption. But now try double the supply voltage.

In fact at a specific gate voltage, and more than a couple volts on drain, the (MOS)FET acts a lot more like a current limiter. Drain current will change very little over a wide rainge of drain voltages. Not current-proportional-to-voltage like a true resistor.

1K     -2,36v   4.5mA
10K    -2,11v   0.45mA
100K   -1,92v   0.045mA = 45uA
1M     -1,75v   4.5uA
10M    -1,39v   0.45mA

[PRR]

> there is a threshold voltage for Vgs below which nothing happens.

Same is true for JFETs except the threshold voltage is negative (for common N-type). In a JFET "nothing happens" for gate below -3V. Go through -3V to 0V and even +0.5V, current increases. Above ~~0.5V the gate diode sucks and spoils your high input impedance, power gain, and general usefulness. There "are" MOSFETs which have negative threshold voltages. But positive Vto is more useful, so they dope the gate to shift the threshold up positive. There's no gate diode so you can go +5V even +10V. (Past +20V the gate oxide blows.)

[R.G.]

Yeah.

Junction Field Effect Transistors are what I'd laughingly refer to as "garden hose effect" devices. The channel is a resistor made from doped silicon. In the absence of any electric field from the gate, it conducts like a silicon resistor. The gate is not really a single pin, it's a whole blanket over the conductive channel. If you connect the gate to the source,  and current flows, the gate voltage is constant, but the voltage along the channel is not, and this starts a cascade of effects that wind up pinching off conduction in the channel. This pinch-off is just like stepping on a section of garden hose to cut water flow.

Mostly. In JFETs, the gate is isolated by being the opposite polarity of the silicon in the channel, and it's isolated by reverse biasing the gate. The reverse bias cuts current flow by literally constricting the area of the channel which is available for charge carrier flow. Put enough voltage on it and it pinches off the channel entirely.

There is a whole panoply of effects of the gate voltage, channel voltage, source voltage and varying degrees of pinchoff down the channel.

JFETs cannot work as enhancement devices, because the gate would not be isolated from the channel, and the electrical field effect would be lost. So they have to be depletion mode: normally on, turn them off by pulling the gate opposite to the channel polarity.

MOSFETs are a bird of a different feather. They have an isolated gate too, but the gate is isolated by a layer of glass twenty volts thick. So the gate remains isolated for all gate-channel conditions below the puncture voltage of the glass.

MOSFETs then have the freedom to have the channel doped as either a depletion mode (i.e. normally conducts, use the gate to turn it off by pinching it closed), enhancement mode (dope the channel very lightly and a region under the channel more heavily, and have the gate attract charge carriers into the channel and make it conduct more as you enhance the gate to pull in more charge carriers) or even zero biased. This weird duck conducts some with the gate at the source voltage, conducts less as you make it more negative (for a N-channel strange duck) and conducts more like an enhancement device as you make the gate positive. You can't play these tricks with JFETs because the gate isolation is by reversed diode junction.

So it depends on your viewpoint. JFETs really are normally conducting, and you have to do something to turn them off. Enhancement mode MOSFETs really are non-conducting until you do something to make them turn on. But I suppose it's OK to think of the JFET as having a "normally off" condition as long as there's a few volts negative on the gate.

[PRR]

> Junction Field Effect Transistors are what I'd laughingly refer to as "garden hose effect" devices.

A good approximation.

> So they {JFETs} have to be ... normally on

Define "normal".

In JFETs, yes, the gate current is non-neligible and if we do nothing else, they reliably turn ON.

OTOH in MOSFETs the gate current is incredibly small and no special direction. A naked MOSFET can be in any state. There's no "normal".

Conventionally we have a resistor to "common", which is also generally the Source, so they tend to go to that "zero-bias" point.

The difference JFET and MOSFET (aside from gate current tendency) is only in an "offset voltage" on Vto. For several reasons N-type JFETs have a negative Vto. In MOSFETs the Vto is under control of the guy with the dope. Negative (in N-type) Vto is possible. In most circuits, this is as awkward as it is in JFETs (need negative Gate bias or a positive shim under the Source). Most systems in the last 40 years use a single supply positive of common. It would be convenient if the "something happens" point is positive. Dope (or ion implantation) is used to add a static offset to Vto to make this happen. This is not a precision process. Big old devices might have Vto at +5V and not approach melt-down current to +10V. That was awkward in a 5V world so now most devices have Vto near +2V and are gushing at +4V. In non-power applications (CPUs) the rails may be under 2V and Vtos are doped to a part-Volt.

And as you say, there are a couple MOSFETs doped for Vto a bit negative, some reasonable current at Vgs=0. Handy for current regulators and a few other things.

If you assume "zero V is normal", then JFETs and MOSFETs may be likened to spring-loaded water valves. JFETs are normally on, you push the handle down to reduce flow. All-purpose MOSFETs are made to be normally-off, you lift the handle to increase flow.

Stephan has plotted "handle-position versus flow". 2.6 millimeter lift will wash a cat, say. 1.9mm will wash a mouse. 1.4mm will wash a flea. Valuable information. Of course as on drinking-fountain valves, every one is different. If he goes through a bag of valves he may find the mouse-wash position 1.9mm or 1.6mm or 2.3mm. In drinking/washing we are accustomed to adjusting the flow manually. In electronics we find ways to make the actual gate voltage somewhat self-adjusting. 

[R.G.]

> So they {JFETs} have to be ... normally on

Define "normal".

In JFETs, yes, the gate current is non-neligible and if we do nothing else, they reliably turn ON.

In this case, "normal" is "if we do nothing else".   

In JFETs, we can make the gate current be zero by leaving the gate open. Unless someone has played games with the internal doping and metalization, this runs the gate current down to nearly zero. The only non-zero-ness is the voltage generated by the voltage down the channel. Since the channel is more heavily dopes (i.e. more conductive) than the gate, the gate largely sits this one out. Rds with the gate open is pretty much the resistance of the doped channel. This makes the channel a resistor you squeeze shut with the gate voltage, at least until the voltage distribution down the channel starts pinching off increasing lengths of the channel.