CMOS noise (not pop!)

[MrStab]

Hi,

i was wondering if anyone could point me to, or explain, the basics of the noise inherent to CMOS chips - particularly switches such as the 4066 or 4053. i don't mean switch popping, i think i mean 1/F noise. is it inevitable to an extent, like how some folk suggest hand-picking inverters for least noise in the Red Llama etc.? there's so much confusing or conflicting information out there, and the documents that do seem to answer my question are way above my level.

i've basically run into a problem where a 4053 arrangement just won't play well within a resonant filters. the switching itself is fine, it functions as-intended with negligible pop, but there's a hiss i pretty much have to attribute to the 4053 at this point. i'm only connecting low-Z outputs and high-Z inputs (ie. direct from/to op-amp pins) to the switching IC. i've only used 4053's from the same batch, but unless there's a widely-available variant of the chip for audio use (i did hear there was a Phillips one), i'd rather take it out completely.

anyways, i'm about to just replace it for a 3PDT, so i thought i'd ask in case there's anything else i could try, but moreover because i could only find scattered info online, so maybe you guys could clear it up here for future generations *checks News* i mean for us

cheers!

[R.G.]

I think there may be something else going on in your circuits.

CMOS does have thermal noise, flicker, and shot noise, like all amplifying devices. However, I've used the 4053 literally for over a decade in commercial designs without noticeable hiss problems. And our customers are not shy about telling us about any flaw, real or imagined, so I think I'd have heard about it if there was an issue.

But it is always possible that you've run into issues that I haven't encountered yet.

I think it's get-out-your-oscilloscope time. Actually seeing the noise would help a lot in finding the cause. Here are some possible issues I can think of:
- provenance of the CMOS chips you are using; you mention they're all from one batch. Try a different brand, especially if these were obtained from a surplus source or ebay. They may be fallouts for some reason. Try a few from a reputable dealer that is worried about counterfeiting.
- power supplies; you don't mention your power supply limits. CD4000 series devices usually will go to 15V, sometimes to 18V, or +/-7.5 to +/-9V. Other series, especially the 74xC4053 and the like may have power supply specs down in the 5-6V range, but be otherwise pin compatible.
- ultrasonic or RF oscillation; both of these can sometimes make for an angry-sounding hiss that can't be otherwise tracked down as the phase jitter in the RF heterodynes down into audio. Something like this is especially suspicious when you talk about using resonant filters. Resonant filters are inherently almost-oscillators; that's why they resonate. It doesn't take much to push them over the edge, sometimes at a frequency that you didn't expect.
- open inputs on the CMOS chip; CMOS inputs are so very high impedance that any open input can pull in hum or RF from the air and make for very odd issues. Never, ever leave a CMOS input pin floating. Always tie them to logic high or low.

The business about hand selecting inverters for low noise makes sense - inverters are digital devices that can be forced into an analog perversion of what they were designed for. So it makes sense that their noise characteristics were not even a thought on the designers' horizon. CMOS analog switches are definitely a part that got analog signal consideration, so it's unlikely that they were designed without those considerations, and hand selecting CD4053s is much less likely to be needed.

[anotherjim]

In what circumstances are you getting noise? I think ideally the signal doesn't want to be too small or the switch placed between high impedances. Especially on a bread board, the high impedance of an "off" switch can allow noise pickup. So a little pre-gain (x3) and low impedance if possible after the switch. So, op-amp x3>switch>10k input impedance op-amp; should be a clean path and with both amps on the same Vref, no need for AC coupling & bias resistors on the switch.

Linear inverters is another matter. With high value feedback R as is often done, the idle gain can be very high producing a lot of noise. However, the S transfer curve means that gain falls off as signal swings toward either supply rail. This results in the noise level pulsating about the zero crossing. You can see it on a scope. A small feedback cap can make it a little less obvious.
Personally, I feel that if the aim is to get the soft clipping characteristic, it's best done by feeding the inverter a large signal from a clean amplifier and give the inverter only moderate (not more than x10) gain with a lower value feedback resistor. They are not particularly noisy in this situation. It won't sound quite like a Red Llama though.

[MrStab]

thanks for the replies guys. i don't have a full schem just now but here's a rough overview:

like 90% of my posts these days, this is about a circuit more-or-less like Fig. 5 here: http://sound.whsites.net/articles/state-variable.htm

two of the switches put the Q pot in and out of the circuit by shorting it to Vb, another switches what goes into the state variable diffamp (non-inverting pin on U1A in Fig5). BP goes straight to U1A, whereas HP/LP go via. an inverter to get the right phase. seems to crap out otherwise. hiss happens in both states and in all SVF settings. there are no open pins, the GeoFex article taught me that's a big no!



the brand i'm using is TI, specifically the CD4053BE, and i do consider it to be from a trusted supplier, but i'm open to the possibility of duds. Supply voltage would accomodate both 9V and 18V supplies (iirc some 4053's go up to 20V), but i've only tested with 9V and 15V thus far.

i've tried bypassing every IC's power pins with 100pF-100nF ceramics, to no avail. i've also tried limiting the bandwidth, which does help to some extent if i roll-off beyond 5-10KHz (probably ruling out pink noise), but i need to reach up to 20KHz for the handful of acoustic users. on every op-amp outside the state-variable filter stage, a ceramic rolls off around 21KHz.

there's some initial pre-gain of around 3 to get above the noise floor. whether i boost the whole range, or just the higher frequencies for pre-emphasis (compensating later), there's no major improvement. the problem's still there if the input/output stages are at unity. Vref is buffered, by the way.

i've made 2 versions (3 if you count the initial spaghetti one) with different layouts, to try and rule that out. i've made up to a hundred circuits without the feature that requires the 3PDT, and none of those had the issue. relocating and using a different amp doesn't help at all.

not the best-structured post, but there you have it.

cheers for taking the time!

[MrStab]

hmm, okay: the CD4053 removed does reduce hiss somewhat, but not as much as i thought it would. so i'll try to figure the other cause out. i'm still curious about the CMOS noise though, what Jim described sounds like it'd be handy to get my head around.

FWIW, it's not insane mega-hiss, but it is something a clean player might object to, especially over 3 bands. just using 1 at the moment.

...in fact, i'm starting to suspect an issue with the MG amp i'm testing with. the previous layout had issues on a known-quiet amp, which threw me off that possibility (but that had to be fixed either way or i'd be dealing with 2 problems!). i'll test on a Marshall DSL100 and report back tomorrow. the 4053's contribution to the noise may be minor enough to keep using it.

[Rob Strand]

i've made 2 versions (3 if you count the initial spaghetti one) with different layouts, to try and rule that out. i've made up to a hundred circuits without the feature that requires the 3PDT, and none of those had the issue. relocating and using a different amp doesn't help at all.

Shorting the Q  pot like that does have its issues.  There a large noise gain at U1B ie.
U1B operates in high gain and any noise from the switches is amplified.  I'm assuming R6 is left in, as without it things are a lot worse.     I put my money on this part of the circuit.


As to why the switches are noisy I'm not sure.    To get noise they might be high resistance but if they are high resistance then you don't get the noise gain.

CMOS switches don't switch all the way to the power rails.   How is the power of the CMOS switches and the OPAMPS set up exactly?  Also is it dual supply or single?

[MrStab]

by looking at it, i'd expect some sort of disaster to happen by switching that pot out, just based on location, but surprisingly it has a minimal "click" when switched (with the 4053) and it probably only accounted for 5-10% of the noise. R6 is left in. it's single-supply, sorry for leaving some of this out. the V+ on the op-amps and CMOS are all on the same rail, if that's what you mean? probably not what you meant! lol

i THINK i've figured it out, but i'm not sure if this warrants another thread. the reason for my whole redesign was because while people liked my EQ pedals, a recurring complaint was lack of recovery gain. the initial plan was to boost a little bit before the EQ stage, to get above unity for noise and the user's sake. as an experiment, i tried a compromise between emphasis and recovery gain, namely boosting everything above 2.5KHz in advance, then boosting everything below 2.5K afterwards (instead of attenuating what i'd boosted at the input). just now, i made the input stage cover the whole spectrum, and reduced the output stage to unity (both non-inverting amps). hiss has gone way down.

so with or without the bandwidth limiting experiment, the output gain stage seems to be the cause. the last iteration was a b****** even with everything at unity, so i must be making some progress! i'll stick another 4053 back in there and see what happens tomorrow. i think i have another batch from Rapid Electronics, not sure what brand they use. maybe the reduction in gain will mean the 4053 is no longer even a small issue.

cheers! i'll let you know how it goes. i still need to look at my amp, which was adding its own small-but-annoying noise on top of this one.

edit: in hindsight, it was stupid of me to try the bandwidth test when i was trying to rule out layout (then CMOS) problems. fortunately i got "lucky" and it was the gain stages generally at fault.

[dschwartz]

I had a similar problem when designing the omnicabsim..i also blamed initially on the cd4066 i was using for bypass...and then realized it was related with gain..for some reason i don't fully understand, i was getting a lot of hiss from a boost stage at the end of the circuit..
Moved the stage before the circuit and the hiss was gone..

[anotherjim]

Rapids 4053 are TI at the moment, which I assume are to the normal CD4xxx spec's.

I think the worry is that the signal swing can exceed the switches range of low distortion operation. However, maybe, the fact that TL07x amp outputs can't swing rail to rail anyway might mean that's somewhat moot?

One thing with buffered Vref, the resistive divider must still have bypass caps to keep it clean, otherwise power supply noise is injected into the reference.

[MrStab]

kinda off-topic, but i've had some major realisations lately and i'd like to mention that the whole inverter thing with the SVF diffamp is wrong. probably a no-brainer, but it took me well over a year to realise: the function of the Boost/Cut pot is entirely-dependent on the SVF output's phase. the ESP article mentions this in passing, but not in-depth. some of the Rane articles probably cover it in an alien language.

with the Boost/Cut pot set in the middle, the BP output (U2A) is a full half-cycle out of phase with the input signal, hence no effect at 12 o'clock. the HPF and LPF (U1B and U2B, respectively) are 90 degrees off on either side, and must be shifted to also be 180 degrees out-of-phase with the input. there are probably a few ways to do this, but i seem to be having luck with fixed integrators at the moment.

at some point i'll write up a proper post on all my state-variable filter learnings for people as dim as myself. this post is 5% to correct my error for posterity, 95% because i'm just really stoked that i figured this out! whoever came up with that has blown my mind.

back on topic: with corrections, the 4053 doesn't seem to be adding any considerable noise to the signal. i'm currently using LM662, as i had a couple laying around, and the noise went way down compared to the TL072. so i might try some OPA*134s in there.

there are three 47uF caps to ground on the Vref line, as the circuit is spread over one board per band. i'd imagine the non-R2R op-amps to be "protection" against the CMOS clipping too, Jim. unfortunately, i wanted to use TLC27*s!

seems moving the gain solved my problem, too, Daniel. i also placed the high band last this time, so it wouldn't collect noise through two subsequent stages.

cheers!

[Rob Strand]

There's quite a few variants of state variable based parametrics.   Not all are good.   
- Some have noise gain issues
- Others have internal overload issues (ie. some internal node in the circuit overloads.).   
- There's variants with dual pots for the Q and ones with single-gangs
- There's also differences in how the notch works some produce a symmetric boost and cut (on a dB scale)
   and others produce a notch which narrower than the boost.

I looked at this stuff in detail years ago.   State variable filters can also be used for oscillators.
The rane stuff is usually pretty reliable.  However after Bohn come-up with the "constant Q" thing (maybe in the 80's) I think their designs move along this path.

[MrStab]

i drew the line at the standard Urei 545 (single Q-pot) configuration when i found myself mailing a South Korean retailer about their centre-tap pots for the Gain a year or 2 ago. no reply. i decided then i should have a long, hard look at my life. lol

i've made loads of em but have only really looked under the hood to this extent in the past few months. if i get round to making a big post, and i remember, i'll send you a draft to proof-read (or even contribute to) if you're interested, Rob.

[Rob Strand]

if i get round to making a big post, and i remember, i'll send you a draft to proof-read (or even contribute to) if you're interested, Rob.

Sure, I'll be happy to look over it.

[anotherjim]

there are three 47uF caps to ground on the Vref line, as the circuit is spread over one board per band. i'd imagine the non-R2R op-amps to be "protection" against the CMOS clipping too, Jim. unfortunately, i wanted to use TLC27*s!

Now I ask (because I don't know for sure), if having bypass caps on the output of a reference buffer is necessary, or even a good idea?
1: We know op-amps don't like capacitive loads and some R should be inserted if that's the case, or else they can be unstable.
2: Design references are strangely unhelpful, they rarely show the circuit beyond the reference op-amp output and don't, at any rate, show any capacitors on the output.
3: For sure, you should have filter caps on the resistor divider feeding the reference amp.
4: A good op-amp has very low output impedance - would bypass caps to make any difference anyway?
5: If there is a need for bypass caps on the reference supply -  should they be balanced? Cap's to 0v AND of equal value to +V.

[Rob Strand]

If there is a need for bypass caps on the reference supply -  should they be balanced? Cap's to 0v AND of equal value to +V.

It is generally better to only bypass to ground.   
The reasons are:
- a single supply uses ground as a reference so you want all the refs to be AC connect to ground (and clean)
- A single ref cap to ground acts a filter to all junk on the +rail, even hum.   When you put a second cap to the +rail it injects half of the junk into the lines connecting to vref and so injects the junk into the inputs of all devices which have ground referenced inputs (ie. the first stage and all stages with feedback path to ground).

One exception is when you need to pull a lot of current from the ref line - but then you probably need a buffer.

A spin-off of this is it is generally better to connect the feedback paths to the ref point instead of the ground.  This has an added bonus for SMD designs as it avoids unnecessary DC bias across the caps.