PT2399 Question... Pins 7 and 8

[lapsteelman]

Could anyone explain what these pins do on the PT2399? The data sheet calls them current control 1 and 0.. I know they are usually connected to ground through .01uf or .1uf caps...

I can get the chip to work fine in circuits, I'd just like to understand it better..

http://www.princeton.com.tw/Portals/0/Product/PT2399_1.pdf

[merlinb]

http://www.diystompboxes.com/smfforum/index.php?topic=86297.msg724260#msg724260

[anotherjim]

Unless we have someone who knows the chip internals, it's mostly conjecture. 
However, looking for simple 1bit systems found me this page...
http://electronicdesign.com/analog/low-cost-audio-delay-line-uses-1-bit-adc
This is the diagram...

One of the few references I found with what looks like a real-world circuit.
Those caps may be same function as those Cx?

Starts me thinking "could I hack a PT2399 work-alike with short enough delay for flanging & chorus?"

[highwater]

Starts me thinking "could I hack a PT2399 work-alike with short enough delay for flanging & chorus?"

I like it, and it could certainly be done... but there's always a "but".

I'm going to assume for the rest of this post that a flanger sweeps the delayed line from 1ms to 10ms. The PT2399 has 44k of memory, and a published range of ~32ms to ~320ms. This works-out to about 128kbit/s at a 2MHz clock, and about 1.3Mbit/s at a 20MHz clock... so if we expect similar fidelity to a PT2399, we'd be wanting somewhere in the 8kbit-12kbit range.

So, how big of a shift register can we get? All I know (at all) is the 7400-series and 4000-series, so lets see what there is there. The 7400-series seems to max-out at 8-bit shift registers, so that's a no-go (may as well build a discrete BBD at that point). The 4517 is the longest in the 4000-series as a dual 64-bit, so if we keep in the same clock-speed range as the PT2399 we'd need 10 of 'em to get a 1ms-10ms sweep. BUT, that ends-up being more expensive (like $5/ea, and no easier to find) than a real BBD, and the datasheet shows a max clock of 3MHz-min/6MHz-typical at 5v, 6/10MHz at 10v. Hmmm, not going to be making a monolithic flanger-appropriate clone of a PT2399 at those specs...

...but, as much as we like it, this is only rock-and-roll, so we can probably go a bit slack with the specs. Obviously, the necessary high-end roll-off at a lower clock-rate is going to limit the upper-end of the notches, but I assume that as long as the clean signal is clean, the delayed signal can be pretty lo-fi and still give flanging. Is it going to sound the same? Nope... but I'm sure it'll work better than a PT2399 that latches-up from trying to run it too fast. And, again, it's rock-and-roll, so a different sound can be good more easily than it can be bad.

So I'm thinking that as a proof-of-concept, that circuit with four CD4517s in series and a clock cycling somewhere in the 500kHz-5MHz range would probably be capable of giving a passable flanging and/or chorus effect.

Only problem is, all the effort/time/money taken to design and build the thing would probably cover an actual 512-stage BBD and a circuit of proven quality to plug it in to (or a flanger, a chorus, *and* a delay w/ 1024-stage BBDs).

P.S. - I *started* typing/researching this assuming that leftover 512-bit DIP8 shift registers could be found at pennies on the dollar. I really thought it was going to end-up being more optimistic.
P.P.S - The other route would involve a normal RAM chip and a memory controller. Probably not a much better idea right now, but that route might actually be reasonable in a future without BBDs.

[anotherjim]

I thought the shift register would actually be a DRAM chip, 16k x 1bit was a common size and the world is probably still full of them, even if they are obsolete. Addressing done by binary counters.
Certainly not as easy as BBD, but maybe a fun project.

[highwater]

I'm stuck thinking of DRAM as adding extra complexity by needing refresh... didn't stop to think that in this case it's being read and written fast-enough for that to be un-necessary.

Given that, it probably *would* be comparable in complexity to a BBD flanger... at-least compared to a BBD flanger with a homebrew clock-generator. Even with a modern, x8bit DRAM you could just ignore all but one bit, so it would be easily adapted to currently-available parts if the 16k x 1bit supply is/goes dry.

[EBK]

Forgive me if I'm being naive, but is DRAM refresh still considered complex or cost-inefficient today? (I'm under the impression that it's not)

[anotherjim]

No, DRAM refresh isn't really difficult, but forms of static (and non-volatile) memory are simply getting cheaper and easier to implement. You don't find much DRAM in embedded systems and such-like. PC memory DIMMs are still DRAM aren't they?

Refresh would just add complexity to a DIY delay if the addressing cycle was too slow. If the Row addresses are sequenced through fast enough, I don't think you need any additional refresh access.

[slacker]

P.S. - I *started* typing/researching this assuming that leftover 512-bit DIP8 shift registers could be found at pennies on the dollar. I really thought it was going to end-up being more optimistic.

I had the same thought a few years back after I got intrigued as to how the PT2399 worked and simulated it in LTSpice. I forget the part numbers but remember finding some likely looking FIFO chips but they were all obsolete and virtually unobtainable.
For short delays you could possibly use a smallish micro controller as the memory or use it as the interface between the comparator and the memory, that's basically what the Boss DD-3 does.