Sadowsky bass preamp clone troubleshoot

[subnormalwater]

Hello everyone, I'm trying to build my 3rd diy pedal but every time the final result is not working 100%. 

I followed this board: http://johnkvintageguitars.homestead.com/Effects/others/Sadowsky/SadowskyBassPreamp.png

Which is mostly based on this schematic: http://theernie.com/wp-content/uploads/2014/10/Screen-Shot-2014-10-16-at-11.05.05-AM.png

Modifications made to the board: removed the zener diodes ad placed the 47pf at the first gate (as the schematic) (optional 10k and 1nF not placed as the board layout - shorted opt.10k of course)

Alright;

I can't have almost any signal passing through the first fet, everything sounds heavily distorted and super low volume, I can hear something by cranking up the gain on my amp and still having troubles getting something out from it. I kinda solved that by placing a 47k between the gate and ground;

Now I'm stuck at the 2nd gate, I have signal passing through the 100nF but if I link it with the gate everyting goes mute (well.. super low volume with distortion like before)

I checked the 100nF, 1M resistor and the 300pF, they are fine, I just can't understand what's going on with this pedal, I already replaced the fets two times 

At stock I'm reading 3V on each drain, by increasing it to 5V (another 10k in parallel) the volume goes up to normal but still distorted and the signal struggles to get through.

All pots connected except the volume one, it's just 100% all the time.

Tell me if you need some other readings, I really can't understand why I'm struggling so much on this simple build!

[Rob Strand]

Sounds like a biasing issue.

What JFETs are you using?   IIRC, the original used 2N5457.

At stock I'm reading 3V on each drain, by increasing it to 5V (another 10k in parallel) the volume goes up to normal but still distorted and the signal struggles to get through.

Probably 6V is about optimal although 5V shouldn't be bad.

The best way to tune the biasing on that circuit is to trim the 10k in the top left corner.  You should be able tune both drains to reasonable voltages simultaneously.

If you are using J201's the bias might be harder to set.  It might even be hard to get both to bias correctly unless you play with some drain resistors.

[Rob Strand]

OK, I see the problem.  You need to add 1k resistors in series with both 47uF caps.

[subnormalwater]

Using 2n5457, sorry.

Let me show you what I get, I just noticed something odd (stock/no 47k or other changes):

1st FET:

D:  3.169V
G:  0.786V
S:  3.069V

2nd FET:

D:  3.109V
G:  3.076V
S:  3.079V

Just saw your reply, I'm going to try that

[subnormalwater]

OK, I see the problem.  You need to add 1k resistors in series with both 47uF caps.

no success

[Rob Strand]

1st FET:

D:  3.169V
G:  0.786V
S:  3.069V

2nd FET:

D:  3.109V
G:  3.076V
S:  3.079V

Hmmm those measurements look crap!

The layout matches the 2N5457 pin out so it's not a pin out issue - it doesn't hurt to check.

What voltage do you measure at the bias divider (100k+10k + 100n) in the top left of the schematic?

no success

While it's not the problem here, I do recommend leaving the 1k's in.  The original is like that and it will prevent clipping, especially when the battery gets low.

[Edit:  check for shorts and any track cuts you have missed.

The fact the two gates are at different voltages is maybe the key. Check around those.]

[subnormalwater]

Hmmm those measurements look crap!

The layout matches the 2N5457 pin out so it's not a pin out issue - it doesn't hurt to check.

What voltage do you measure at the bias divider (100k+10k + 100n) in the top left of the schematic?

The pinout is correct.
Reading 0.85V right after the 100k. It's a 100uF btw.

While it's not the problem here, I do recommend leaving the 1k's in.  The original is like that and it will prevent clipping, especially when the battery gets low.

[Edit:  check for shorts and any track cuts you have missed.

The fact the two gates are at different voltages is maybe the key. Check around those.]

Isn't the second gate supposed to be higher? it's directly connected to the drain of the first one, measurement made with 100% on both pots

No shorts, I'm going mad at looking for them.

[Rob Strand]

Reading 0.85V right after the 100k.

It's "OK" but it's probably a little high *because* the gate voltage of the second JFET is high.

It's a 100uF btw.

So it is.

Isn't the second gate supposed to be higher? it's directly connected to the drain of the first one, measurement made with 100% on both pots

The two stages are identical so they should bias identically.

Maybe the best place to look is around the date of the second JFET.   That's the weirdest measurement at this point.   It is possible DC from the drain of the first JFET is getting through to the gate.  So maybe check around the 100nF on the gate of the second JFET.

[Rob Strand]

No shorts, I'm going mad at looking for them.

On the layout there the 5th track from the bottom has a cut, just under the 750ohm resistor.
The track would join the drain of the first JFET to the gate of the second.

[Edit: I simulated this fault and it shows similar voltages to yours.]

[subnormalwater]

On the layout there the 5th track from the bottom has a cut, just under the 750ohm resistor.
The track would join the drain of the first JFET to the gate of the second.

[Edit: I simulated this fault and it shows similar voltages to yours.]

I'm doing it on a perfboard, I did all the tracks by hand, everything on that gate is correct 

I tried to desolder everything from the gate and I still read 3V from the pin itself. Is it ok? I'm extremely ignorant

Voltages from 1M and 100nF are correct

[Rob Strand]

I tried to desolder everything from the gate and I still read 3V from the pin itself. Is it ok?

If the gate is floating then it's probably OK.  3V just means the JFET is fully on, like a short.  When that happens the 10k and 5k fomr a divider giving 3V;  9*5k/(5k+10k) = 3V.

OK what about if you now connect the gate(s) to ground.  That will tell us the JFET is "working".

I'm extremely ignorant

No.  Debugging can be tricky.  You have theory and pursue it.  If it fails use that info and move onto the next theory.  If it gets too hard divide the problem, ie the region of the circuit, down then debug the smaller piece.  Eventually you will find the problem it just takes a bit of persistence.

[subnormalwater]

If the gate is floating then it's probably OK.  3V just means the JFET is fully on, like a short.  When that happens the 10k and 5k fomr a divider giving 3V;  9*5k/(5k+10k) = 3V.

OK what about if you now connect the gate(s) to ground.  That will tell us the JFET is "working".

Drain 0.900V
Source 0.845V

edit: sorry, it's just the second jfet.

[Rob Strand]

Drain 0.900V
Source 0.845V

Well that's a bit unexpected.
Now you've got me going Ahhh.

It's like the pinout is wrong.  You only expect to see that if you gate pin is actually a drain or source.
Have you got the flat-side of the JFET pointing to the left, like on the layout?

 

[subnormalwater]

Well that's a bit unexpected.
Now you've got me going Ahhh.

That's how I'm feeling every time it doesn't work 

It's like the pinout is wrong.  You only expect to see that if you gate pin is actually a drain or source.
Have you got the flat-side of the JFET pointing to the left, like on the layout?

Flat side to left like the other one, just checked and it IS a 2n5457 (just to be 100000000000000000000% safe).

[subnormalwater]

Well, it's 1.20AM and I think it's enough for today.

I'm sure it's going to haunt me in my dreams

Thanks anyways, Rob 

[Rob Strand]

Well, it's 1.20AM and I think it's enough for today.

I'm sure it's going to haunt me in my dreams

Thanks anyways, Rob

No problem.

At this point, for my own sanity, I'd pull one of those JFETs out and check the pinouts with a multimeter.   Using diode test, one pin to the other two (one at a time) will look like a diode.  It will have 0.7V in one direction and nothing in the other.  That pin is the gate.

Between other two pins, with the identified gate floating, you should see a few hundred ohms in both directions.

[subnormalwater]

Ok then.

Diode checking:

(com > red)

1  >  2 : 0.062V
2  >  1 : 0.062V
2  >  3 : 0.738V
3  >  2 : 0V
3  >  1 : 0V
1  >  3 : 0.738V

Resistance:

1  >  2 : 37.5R
2  >  1 : 37.5R
2  >  3 : 6.45M
3  >  2 : /
3  >  1 : /
1  >  3 : 6.45M

Well, at least the pinout is correct

[subnormalwater]

Oh God.

The second Jfet had a problem on a leg, by moving it around I got 1.2V to gate in the opposite direction, that's why the second gate was so high 

Now they are biased at the same way but still 3.1V on the drain and very weak signal coming out from the fets

[Rob Strand]

Well, at least the pinout is correct

Now they are biased at the same way but still 3.1V on the drain and very weak signal coming out from the fets

OK great, looks like you have sorted out some of the crazy stuff.

If you can, short out the 10k bias resistor, the one near the 100k in the top left of the schematic.   This is the same as setting both gate voltages to zero.    Then measure the voltages on the JFETs.     We need to do this test again because of the connection bug.    What this does is give me an idea of the biasing and JFET.

At this point I can only think of shorts, missing cuts and maybe wrong resistor values.   See how you go with the re-bias test and we'll take it from there.

[Edit:  1  >  2 : 37.5R
2  >  1 : 37.5R
These are actually quite a bit lower than I expected.
So *maybe* the JFET is low resistance and that is causing the issue.
The only solution then is to change the biasing.
]

[subnormalwater]

I completely rebuilt the whole pedal following a similar board made by the same guy with the addition of a 330k from input to gnd.

Still 3.1V on drain and triple-checked everything, I read the reviews of this pedal and turns out I'm not the only one who's struggling on biasing these 2n5457 

By shorting out that 10k I get around

G: 0V
S: 2.5V
D: 4.2V

G: 0V
S: 3.0V
D: 3.2V

still s#@t on 2nd fet, can't understand why..

EDIT:

[Edit:  1  >  2 : 37.5R
2  >  1 : 37.5R
These are actually quite a bit lower than I expected.
So *maybe* the JFET is low resistance and that is causing the issue.
The only solution then is to change the biasing.
]

Yeah, I think the only way to get a proper biasing is to rebuild that part from scratch.. but I don't even know where to start (dumb_doing_electronics.jpg)