J201 JFET Bias Adjustments

[Rob Strand]

The idea: 
- We start with a reference J201 preamp circuit which is based on a J201 JFET with typical specs.   There's nothing special about the circuit other than choosing to set the bias point on the drain at 5V.
- We then look at what happens when we use other J201 JFETs which are at the extremes of the specifications.  We then try to adjust the resistors to get the same performance as the reference circuit.
- We look at three cases for the allowed adjustments:
1) We make adjustments to RD only.   Here the adjustment tries to set the bias point to VD=5V.
2) We make adjustments to RS only.   Here the adjustment tries to set the bias point to VD=5V.
3) We make adjustments to RD and RS.  Here the adjustments try to be as close as possible to the reference
design.  We try to get the bias point VD=5V, make the voltage gain AV close to the reference and we restrict the minimum Vgs bias point to be more than 0.15V (the reference design is about 0.23V).   The aim of the last point is to ensure there is sufficient input swing.

To compare the designs
- The left column is the reference design in each case.
- See if we were able to set VD=5V
- See how much the gain Av varies for the different JFETs
- See if the the Vgs bias point is too small.  Meaning the preamp could clip at the input.

I want to point out that you never get three parameters Vp, Idss and Yfs all at the extreme tolerances.  In general you only get two at a time as the one of the values is mathematically related to the other two.   The first table at the top shows the JFET tolerances.  The second table shows what tolerance extreme is active for that column.  "Lim" means the value limited by the other two parameters not by the min/max tolerances.

Bypassed means the gain with the source resistor bypassed with a cap.  Unbypassed means the gain when the cap is removed.

There is a comment at the bottom highlighting any funny stuff, like the adjustment is not possible.

Notice the large variations is the gain Av even though you have adjusted for VD=5V.

Here's the circuit:



The results for varying RD:



The results for varying RS:



And the results for varying RD and RS:



[Edit:  One option I didn't include was connecting the bypass cap to a tapped source resistor.   This gives more flexibility to tune the gain.]

[Rob Strand]

I thought I would add case since many people are probably using the Fetzer Valve calculator.   See the bottom of this page,
http://runoffgroove.com/fetzervalve.html

The analysis below uses the same Rs value as the Fetzer Valve calculator ie. Rs = 0.83 Vp / Idss.
Rd is then adjusted for Vd=5V.

As you can see the Rs value at least allows Vd to be adjusted to the prescribed valued.   Notice how the gains vary quite a bit across the various JFET extremes.  The input signal swing looks OK as well.

[Boner]

Holyhell thank you!!! Do I ever need this information at this point in time

[Rob Strand]

The main thing I wanted to show was even though you set Vd=5V the resulting gain for different JFETS varies a lot and that you can reduce that gain variation by varying both RS and RD.

One criticism of my table is I should have added an output swing check.  JFETs are finicky as there are input and output swing limits.   Consider this:
The maximum current the JFET will pass is IDSS.  So in order that the output can saturate on the negative output swing  IDSS must be larger than Vdd / Rd  (where Vdd is the power rail).  A slightly more accurate requirement (for the bypassed source resistor case) is IDSS must be larger than (Vdd - Vs) / Rd.   

Another way to say this is if the drain resistor is too small the JFET cannot saturate on the negative output swing.   When you forward bias the gate junction that's a whole different issue.   So I should have added the negative output cannot saturate if Rd   <   Rdmin      where   Rdmin = (Vdd - Vs) / Idss   which is approximately Rdmin = Vdd / Idss.

The Fetzer Valve choice of Rs = 0.85 Vp / Idss which is equivalent to choosing |Vgs/Vp| = 0.35,   ends-up choosing an Rd  very close to Rdmin  when you have a 9V power rail.   That means it's *just* saturating negatively.

If we choose  |Vgs/Vp| larger than 0.35 (say upto 0.5) then it does two things:  It causes deeper saturation on the negative output swing and it also gives you more gain.   So it might be worth biasing the JFET with |Vgs/Vp| a bit higher than 0.35 if you want more gain.   The way to do that is pretty easy you just choose a larger Rs than the Fetzer Rs = 0.85 Vp / Idss.    Maybe upto  |Vgs/Vp|  = 0.5 which means choosing Rs = 2 * Vp / Idss.   Rd is tweaked to get Vd=5V or whatever you like.

So there is a reasonably large range of Rs values which are likely to work and also give some ability to tweak your tone.

[GGBB]

I was drawn here by a search and noticed the images were missing because of the postimg move from .org to .cc - so I am posting updated links.

Here's the circuit:



The results for varying RD:



The results for varying RS:



And the results for varying RD and RS:

[Rob Strand]

Thanks.  I think I posted that just before postimg changed from .org to .cc.

[tubegeek]

Thanks Rob, great info.