BJT Buffer Design - Which Components and Why?

[Jolly Jimmy]

Hello all,

I'm very much a beginner at all this (not moved past the breadboard) so please bear with me. I have gathered all the info I've been able to find in relation to this but I'm quite unsure about a few things, so here I am. This is my first attempt at adding input and output buffers to a circuit, my goal is to better understand the choice of components. Much of what you see here results from a hands-on, trial and error approach. So I have a few questions I hope some of you may be able to help me with. You made find I have made a few completely erroneous assumptions!



- Input impedance :

As far as I can tell, the input impedance of each buffer is dominated by R4 and R6 respectively, hence my choice of 1M resistors in this position. But I'm unsure of this and the exact calculation. How do I work this out?
I included R3 at the input as it seemed to rid me of a small amount of radio interference. How does this influence the input impedance?


- The VRef divider components, another few questions :

Firstly, from what I understand, for an emitter follower configuration I want the emitter to sit at Vcc/2. The ratio between R1 and R2 gave me this through R4 and R6 feeding the base of each transistor. For the same ratio between R1 and R2, why choose 10K and 5.6K over 100K and 56K for example? How does one pick the optimal values here?
Secondly, why do I often see resistors of equal value for the divider? This wouldn't get me to Vcc/2 on the emitters.
Something escapes me here.


On the outputs of each buffer :

I chose the capacitors C2 and C4 to give me the desired bandwidth for the following sections. This is also influenced by what follows as far as I can tell. In this particular case the emitter of my input buffer is feeding the base of another transistor biased with a voltage divider. My assumption here is that C2 is creating a HPF at a cut-off frequency defined by the value of C2 and the parallel value of the following voltage divider resistors. Big question mark here!

For the output buffer I used a shunt resistor after the output cap making a HPF, this seemed to filter stray DC that was causing a bypass pop. The series resistor R9 was also included to limit current causing bypass pops. How do these two resistors influence the function of the buffer? (input/output impedance?)
How does whatever the output is plugged into influence the circuit? For example should I worry about the cut-off frequency of the HPF being unduly modified by what follows?


I'm sure you will find some glaring errors in my design and observations, but I am here to learn! What have I missed that should I take into account?

Many many thanks in advance for your time!

[R.G.]

Hi, J.J. Good set of questions. I'll try to help a bit. Please ask questions where I confuse things more than I help.

I'm very much a beginner at all this (not moved past the breadboard) so please bear with me. I have gathered all the info I've been able to find in relation to this but I'm quite unsure about a few things, so here I am.

We all start with exactly the same amount of knowledge - that is, zero - but get to different places depending on how hard we pursue knowing. Good on you for digging in and thinking and trying.

This is my first attempt at adding input and output buffers to a circuit, my goal is to better understand the choice of components. Much of what you see here results from a hands-on, trial and error approach. So I have a few questions I hope some of you may be able to help me with. You made find I have made a few completely erroneous assumptions!

You've wound up with what's called the "noiseless biasing" circuit. Works very well. However, you need a capacitor of maybe 22uF upwards at the junction of the Vref divider to shunt resistor noise to ground. You may also need the Vref to be higher than half the power supply to make up for the voltage drop across the 1M bias resistor and the 0.5 to 0.6V across the base-emitter junction.

How much voltage drop happens across the 1M bias resistor depends on how much base current is needed to pull up the 10K emitter resistor, and in turn that depends on what the actual current gain of the transistor is.

- Input impedance :
As far as I can tell, the input impedance of each buffer is dominated by R4 and R6 respectively, hence my choice of 1M resistors in this position. But I'm unsure of this and the exact calculation. How do I work this out?

The transistor itself has an apparent input impedance of its current gain times the emitter resistor. There's a lot of math and assumptions behind that, but it's a good starting point. In your case, if you have a transistor with a current gain of 100, the transistor and emitter resistor give you an input impedance of 100 * 10,000 = 1M. The 1M bias resistor is effectively in parallel with this, giving you a resulting input impedance of 500K. If the transistor is higher gain, maybe 400, then the input impedance of the transistor and emitter resistor are 4M, and in parallel with the 1M bias resistor you get a composite input impedance of 800K.

There isn't anything magic about 1M as an input impedance, so you might be able to live with the 800K just fine. But there are better ways.

Your first question hits the big issue with bipolar buffers dead center. It's hard to get a bipolar buffer to have an impedance that's high when you have to include the bias circuit loading on the input signal.

One way to deal with this is to take a step sideways. Instead of bypassing the Vref to ground, you can hook a capacitor from the emitter back to the Vref junction, driving it with the buffered signal voltage. This is known as "bootstrapping", and is an old technique for increasing input impedance. It's positive feedback, done in a way that makes the signal voltage across the bias resistor appear to be smaller and therefore less signal current goes through the 1M bias resistor back to the Vref. Less current equals less loading. It's easy to get apparent impedances in excess of 1M, even with smaller and lower-DC -drop bias resistors this way. Takes some more tinkering, though. Bootstrapping lets you lower the bias resistor, raise the base and emitter voltage, and still get high input impedance. There are several posts about this here on this forum.

I included R3 at the input as it seemed to rid me of a small amount of radio interference. How does this influence the input impedance?

It adds 1K to whatever the 1M, bias divider and transistor are doing.

- The VRef divider components, another few questions :

Firstly, from what I understand, for an emitter follower configuration I want the emitter to sit at Vcc/2. The ratio between R1 and R2 gave me this through R4 and R6 feeding the base of each transistor. For the same ratio between R1 and R2, why choose 10K and 5.6K over 100K and 56K for example? How does one pick the optimal values here?

First, there are a couple of articles at geofex.com about Vref dividers. It would probably help for you to read those. This one hits your question most directly: http://geofex.com/circuits/Biasnet.htm

In short, you have to pick the resistors to force the loaded Vref to the right voltage. Your circuit won't have much trouble with that, as you've used a special case of a 1M bias resistor and a very, very high gain bipolar, the MPSA18. The '18 is the highest generally available bipolar that's not a darlington that I know. DC loading of a divider amounts to sucking current out of the divider junction, so you have to make the top resistor smaller in relation to the bottom resistor to compensate for the load, or lower the value of BOTH resistors to make the loading inconsequential compared to the divider current.

Secondly, why do I often see resistors of equal value for the divider? This wouldn't get me to Vcc/2 on the emitters.
Something escapes me here.

You're probably confused by the fact that most people work with opamps, not bipolars. Opamps have generally very low DC bias current, so the divider string resistor value doesn't matter all that much. And opamps generally are used with theiir output in the middle of the available power supply. So opamp circuits tend to have equal bias resistors. Bipolars have bigger input bias values (except your unusually high gain MPSA18) and have to make up for the diode drop at the base-emitter, as well as the fact that if the signal is taken off the collector, the emitter is at a lower voltage, so they need non-equal dividers.

The way you put a bipolar output voltage where you want it is to design backwards from the collector and emitter. In your case, you want an emitter at half the available power supply voltage. A universal truth about bipolars is that the base will be one diode-voltage drop higher than the emitter if the device is amplifying. In your case, you want half the power supply on the emitter, so the base has to be half the power supply plus one diode drop higher. Moving back from the emitter, we have to figure out how to hold the base at that voltage. We do it by using a resistor network to funnel current in. Your circuit uses a resistor in series from Vref to supply the current, so the base end of that bias resistor needs to be at the  base voltage, and the Vref end has to be higher by the base current times the bias resistor.

Now the fun starts.  How big is the base current? Easy - it's the emitter current divided by the DC current gain of the transistor. And we do not know the actual current gain of the transistor very well at all. Bipolar current gain varies from device to device within some manufacturing tolerance, and in the same device with how much current it is passing through the collector, and with temperature. It's common to have a five to one change in base current for different devices at different temperatures in the same nominal circuit.

In the case of an emitter follower, this isn't too bad. You can just increase your Vref voltage by a guess at the base-emitter voltage drop and say to yourself "shoot, that's going to be pretty close no matter what" and you'll be fine. It's much worse in a common emitter gain stage where the variation of the emitter voltage is amplified by the voltage gain of the total circuit, so a little wobble in the base and emitter voltage is made huge.

But in general, the bias divider (labeled Vref in your drawing) won't be equal resistors for a bipolar. Vref is an opamp concept.

On the outputs of each buffer :

I chose the capacitors C2 and C4 to give me the desired bandwidth for the following sections. This is also influenced by what follows as far as I can tell.

Three gold stars to you for that insight. It is absolutely affected by what follows - which is in general unknown. You have to assume what loading what follows will add to make a good selection of the capacitor value.

In this particular case the emitter of my input buffer is feeding the base of another transistor biased with a voltage divider. My assumption here is that C2 is creating a HPF at a cut-off frequency defined by the value of C2 and the parallel value of the following voltage divider resistors. Big question mark here!

No question mark - just more work. Your understanding of C2's value being dependent on the following stage is correct. To size it, you need to either know what the following impedance is, or make a good enough assumption. From the discussion of input impedance for your input buffer above, you have some ways to estimate the impedance of the stage after C2. You can certainly make a good guess. One approach that works if you don't want a specific HPF rollof point is to guess at an impedance, then make C2 big enough, then double it. It's usually sufficient to just make the series capacitor too big for the minimum you think you need. There are cases where too much low frequency passed through can be a problem, but they're less common that not having enough. I generally guess too big on C2 and C4, then go back and correct my laziness if there's an issue in the real circuit.

For the output buffer I used a shunt resistor after the output cap making a HPF, this seemed to filter stray DC that was causing a bypass pop. The series resistor R9 was also included to limit current causing bypass pops. How do these two resistors influence the function of the buffer? (input/output impedance?)
How does whatever the output is plugged into influence the circuit? For example should I worry about the cut-off frequency of the HPF being unduly modified by what follows?

Pull down resistors at both input and output of 1M and over are basic practice, for exactly the reason you mention.

You're likely to become a good circuit designer, given that you seem to have come up with the idea that there is always something before and after your circuit and that will affect things. Some people don't get that. The only complication here is that whatever is at the input and output can affect AC loading only, being isolated by capacitors. They can't affect the DC bias conditions. So the circuits have different AC and DC gains in general. The external shunt resistor appears in parallel to the emitter resistor for AC loading only, as does the sum of the 1K series resistor and whatever unknown load happens from the unknown thing plugged to the output. This composite series/parallel combination makes up the effective value of the emitter loading for AC.

Yep, that affect the base input impedance, because the base impedance is most simply approximated by current gain times emitter impedance. So, just for illustration, if the pull down at the output is 1M, and the input impedance of whatever is plugged into it is 10K, you get an AC emitter impedance of 10K (the real emitter resistor) in parallel with 1M, in parallel with 1K plus 10K. When you compute that out, it's close to 11K paralleled with the real 10K, so you get about, roughly, an AC loading at the emitter of a bit over 5K. The emitter load added by the 10K load plugged into the output has just halved your base input impedance. That may be OK, maybe not. Depends on what input impedance you need on your output buffer. It's a bigger issue on your INPUT buffer, as what follows it in the circuit can make your input buffer impedance not be high enough.

Note that this is now a complication added to the first-approximation of input buffer impedance we touched on in the first question. Yep, it all matters. Good designers learn how it varies, then make simplifying assumptions.

The series output resistor simply adds 1K to whatever unknown impedance is lurking out there.

I am here to learn!

Right answer!!

[PRR]

What he ^^ said.

You penciled "900" for MPSA18 gain; this is the high side of the published specs. If true, 900*10K makes 9Meg. If you get MPSA18 toward the bottom of the spread, 400*10K makes 4Meg, making as R.G. says 800K. Which is fine.

YES re: bypass cap on voltage divider.

> want the emitter to sit at Vcc/2

That's a fine first-dart target. Then you have to allow for windage. Say you were trying to drive a 1K load (with your 10K RE as given). Then you would want to bias "high": the transistor can pull-up fine, but a 10K can't pull-down a 1K well at all. OTOH if you are driving >100K and only hope for a Volt, the "center point" becomes not-at-all critical.

The 1K has negligible effect on input impedance (which is not that critical anyway). Radio rejection is either unimportant or VERY important: a box that plays fine in the garage but craps-out at Truck Stop Lounge (lot full of boosted CB and Police radios) is no good at all. Also: Stuff Happens. Your idiot assistant plugs the input to the speaker line of the 900 Watt amp behind the bassist. You really want "some" series impedance so the input path does not become a freeway for large stray signals. Fender liked 34K in front of 12AX7. In this case I could see 10K. If this is ahead of the 1Meg it causes a small loss. If behind the 1Meg the loss is less (now only the 4Meg-9Meg of the transistor).

Finally: plagiarize plagiarize plagiarize!! Yes, think about why the designer picked "those" values. And pick your plagiarizees carefully; the innernet is full of crap ideas. Commercial products are about 99.44% sure to be at least OK.