Need some help understanding JFETs, Voltage and overdrive

[EBK]

If you forward bias the gate if a JFET, you will start pushing current through the junction as if it were a forward-biased diode, assuming it doesn't simply burn up.   So, yes, clipping* will occur due to this diode effect.  Still, not a great idea to do this because JFETs don't fail in visually stunning ways like electrolytic caps do, making it a rather dull experiment. 

*Edit: I realized I didn't paint the complete picture here.  When you forward bias the gate, you are also injecting current into the channel, further increasing the drain current almost as if the channel were more open (just an illusion), but this gate current isn't modulating the drain current like in a well-behaving amplifier, but rather adding to it.  Also, input impedance drops dramatically.

Edit 2:  I was quite wrong in my analysis.   
See below. 

[GibsonGM]

What I'm curious about is that with no source resistor (how you would normally bias the FET, by elevating the gate, much like a triode/cathode resistor), you have an alternating signal riding on a DC offset.  Unless I'm truly obtuse and missing something, it doesn't cross zero, it's not truly AC....so what is the effect of feeding this to some other device?   Honest question, it's not something I've dealt with.

[antonis]

Now you confused me, Mike..

An AC signal riding on a DC offset is exactly what we intend to do..
(DC bias Base/Gate/OP-Amp input ridden by AC signal.. - superposition..)

Direct signal coupling (no DC offset/elevated signal voltage) is mostly used on symmetrical bi-polar supplies, where signal swings almost equally above and below zero volts..
(you may call it "floating" due to no real grounding..)

Perhaps, I didn't get what you really wonder about..

[EBK]

What I'm curious about is that with no source resistor (how you would normally bias the FET, by elevating the gate, much like a triode/cathode resistor), you have an alternating signal riding on a DC offset.  Unless I'm truly obtuse and missing something, it doesn't cross zero, it's not truly AC....so what is the effect of feeding this to some other device?   Honest question, it's not something I've dealt with.

I'm not sure I completely follow your question.  I assumed that the input was at 0VDC and therefore does cross zero.

In addition to self-biasing, like you describe, you can bias a JFET without a source resistor by applying a negative DC offset to the gate, e.g., instead of a gate resistor to ground, you could have a gate resistor to some negative DC source.

[antonis]

I believe that Mike managed to confused us both, Eric, and happy ever after gone for his beer...

[GibsonGM]

I believe that Mike managed to confused us both, Eric, and happy ever after gone for his beer...

It is day time here, Antonis, 1:30PM...I do not drink beer before 5 PM       Perhaps I NEED to drink a beer!

I took another look (simulation).   I didn't add a load resistor after the output cap     So that left my output floating.  So the final output was showing as a sine wave from .5V to 3V or something like that...offset.

Adding a 50k after it made the circuit behave normally.       

Be fair to me - no load is given on the original schematic!     But I should have known better.  The load would be the amp or the next pedal.   So yes, the circuit is a nice clean boost.   I will be quiet now. 

[EBK]

Did you add any source impedance for the sine wave input in your simulation?

[BuddyPrince]

Thanks Fellas!

I leave the theoretical debate to you guys, that's way above my pay grade at this point... :-)

I built the Fetzer boost on a vero board and it's working quite well!  If the volume on my bass is up too high, I still get a little clipping. I'm realizing just how hot the output is from these active EMG pickups.  They're way hotter than my other active basses, so as long as I run at 50-75% volume on my bass, I'm good.

I couldn't have done it without y'all and I appreciate the links!  I'll spend some time reading those pages and trying to digest it all.

Cheers!

[GibsonGM]

Did you add any source impedance for the sine wave input in your simulation?

In series, or shunt?  I'm assuming maybe 100R in series, to mimic the output Z of the guitar or other source?    I built the circuit as shown.   I left the output floating - my bad! 

Glad it's working out, Buddy!  There are tricks to attenuate at the input and allow you to have your volume on 10...such as a voltage divider (noisier) or using a FET with a higher Vp (pinch-off voltage), or pop in a different 2N5457 if you have one, see if there's a difference. 

With the Fetzer, you can increase the source resistor to lower the gain...it affects the bias in some ways too, tho, so it would be a "by ear" thing. 

[Rob Strand]

What I'm curious about is that with no source resistor (how you would normally bias the FET, by elevating the gate, much like a triode/cathode resistor), you have an alternating signal riding on a DC offset.  Unless I'm truly obtuse and missing something, it doesn't cross zero, it's not truly AC....so what is the effect of feeding this to some other device?   Honest question, it's not something I've dealt with.

It's actually a valid thing to ponder. 

I remember this coming up about 18 years ago on the sci.electronics.design news group.   It didn't get answered.   Trusting spice for answers might be wrong because the model needs a 2D distributed model of the gate diode **.


- If you have Vds at the drain and Vs=0  then there is a gradual drop of voltage down the channel.
- The gate looks like a distributed stack parallel reverse diodes from drain to source.
- The "diode" nearer to the source has the least potential across it.
   We speculate that this diode has a low reverse bias, passes the most current and hence
   probably ties to the gate to the source more than anything.   So that means something
   more like Vgs = 0.

Another thing to ponder is if you have just the channel it looks like a block of silicon and acts like a resistor.  Does placing the gate there affect things?   When we add the gate it has p-material which sucks out a small region along the gate/n-channel interface.  So that would make the resistance a little less than the raw silicon block.  As the gate becomes positive, due to an AC voltage modulate the gate, it would reduce that suck-out region and decrease the resistance.

It's not a simple situation.

[Edit: ** On the other hand it's like this for the normal JFET case where the spice equations work.]

[EBK]

As the gate becomes positive, due to an AC voltage modulate the gate, it would reduce that suck-out region and decrease the resistance.

Can we just stick with n-channel depletion-mode JFETs for now?  hmm.... 

[GibsonGM]

Awesome Rob, LOL!

To cut it right to non-theoretical...WHY NO SOURCE RESISTOR IN THE ORIGINAL?  Doesn't the Rs give the thing more functionality, gives the designer more control?

[Rob Strand]

My Apologies for a stupid post.
I'm having a sleep deficit day.
I've misread source resistor for gate resistor. 
Post fixed.

To cut it right to non-theoretical...WHY NO SOURCE RESISTOR IN THE ORIGINAL?  Doesn't the Rs give the thing more functionality, gives the designer more control?

Gate resistor: When I see that type of thing I always assumed the source, being a guitar or other, has a DC path to ground and provides a DC path for the gate, like the gate resistor.    By not adding a gate-source resistor you aren't loading the source.  Obviously won't work with a Piezo source which is capacitive.

Source resistor:  Not sure
- Naive design
- Delibrate. Using high current for low noise.  Also Vgs=0 allowed since assuming very small input signals.

Doesn't the Rs give the thing more functionality, gives the designer more control?

It lets you get more input signal swing before the gate-source diode become forward biased.
Beyond that you can control the gain (both for bypassed and unbypassed cases).   You can see some of the advantages of adding a source resistors in the Biasing J201 thread I posted a few weeks back.
[Edit:  Not to mentioned reducing the operating current.]

[Rob Strand]

For spice, maybe connecting 10 JFETs (with 1/10th Rds) in series with the gates tied together will give some confidence to the results.
Maybe not that simple.  That's only going to re-inforce the theory.   We need to choose a correct VP that reflects physics, not thoughts!

[EBK]

I finally understand (mostly) that booster circuit, thanks to a one-page IEEE paper from 1964.  A low-res version is available at this link: http://ieeexplore.ieee.org/document/1445202/

The important bit is:

As the gate-to-source voltage is increased a number of effects will occur.  When the gate voltage becomes sufficiently positive appreciable current will start to flow in the gate-to-source circuit, and, if the p gate is relatively highly doped compared with the channel, holes will be injected into the channel, causing, through conductivity modulation, an increase in the conductivity of the region represented by R₁. ....  The diode-resistance network then assures that as the gate voltage is increased the resulting gate current will be distributed among the diodes.

The "R₁" and "diode-resistance network" are in reference to a DC equivalent circuit model illustrated in the linked paper that is pretty close to the diode model Rob described. So, I now also understand what Rob already correctly described above! 

Now, please excuse me while I place strikethroughs in the incorrect stuff I previously posted.   

[GibsonGM]

Hey, glad I'm not alone in looking at this and going "WTH??", he he.    We're having a big snowstorm here in the arctic, and I haven't slept much for 2 days (good excuse).    There are no stupid posts, we just have moments of conflict - what we know vs. what we think we know, assumptions, etc.    To me, that original thing looked almost DC coupled, simply because of the 'missing' Rs.    JFETs are different! 

[EBK]

Did you add any source impedance for the sine wave input in your simulation?

In series, or shunt?  I'm assuming maybe 100R in series, to mimic the output Z of the guitar or other source?    I built the circuit as shown.   I left the output floating - my bad! 

Series, yes.  As the gate voltage increases in that positive input region, the input impedance of that circuit drops exponentially.  I would expect input source impedance to become quite significant and result in squashing the negative half of the booster's output (a bit like asymmetric compression, which could be quite interesting), unless that is somehow balanced out by that conductivity modulation phenomenon.
Nevermind.  I believe I am wrong again because I was still thinking of a normal JFET....

[antonis]

(without interpreting semiconductor physics..)

With V_GS slightly positive, we get maximun Drain current, depended only on channel resistance and V_DD (assuming grounded Source..).
Channel resistance should be considered constant from now on.. (due to the limit minimizing of depletion area)
Any further Gate-Source positive voltage raise should result in no further current raise..(g_m is practically vanished..)
(at least, not proportional to V_GS anymore - Gate to Source forward biased junction current simply adds to Drain current and not amplified in any manner and should be restricted someway, e.g. with a series resistor..)
When V_GS starts to be negative, Drain current "follows" it in a proportional manner (g_m starts to "exist"..)

If so, we might have amplification on both positive & negative waveforms but, for sure, not undistorted..!!

Or do I suffer from another brainstorm..??

[EBK]

The problem is that the jfet stops acting like a jfet, mathematically speaking, once forward biased. In other words, you need a new model and formula (with a gate current term) to explain why the channel conductivity continues to increase. If I understand things correctly, you essentially get a small window of psuedo-BJT (I don't know what to call it) operation, limited by how much power your jfet can dissipate before it fails. 

[Rob Strand]

I finally understand (mostly) that booster circuit, thanks to a one-page IEEE paper from 1964.  A low-res version is available at this link: http://ieeexplore.ieee.org/document/1445202/

Thanks, *extremely* cool find.

There's got to be a region where the Vds drop leaves some of the top diodes reversed bias and the bottom diodes forward bias.  The top would act like a JFET and the bottom maybe like the transistor Cobbold speaks of.  So maybe a cascode model will work.  In an amp ckt I suspect you can only get in this region with low drain resistance values.

The author Cobbold is a famous dude.  He wrote one of  the JFET "bibles".