No Signal out of FET - Troubleshooting Help

[antonis]

However, I'm still left with the question, how do I get the source voltage down to 4.5v?  The bias voltage seems to be int he right range...

You have to set it by Drain current and Source resistor value..
(V_S = I_D X R_S..)

Biasing Gate to a given voltage V_G and for a desired quiescent Drain current I_D, you can estimate Source resistance value needed from transfer characteristics curve of your specific MosFet..
(taking in mind that Source voltage V_S should be slightly more than V_TH below V_G..)

e.g. For a desired I_D of 1mA at V_GS of 3V with 4k7 Source resistor, Gate bias voltage should be on 7.7V for a V_S of 4.7V..
(provided  V_TH < 3V..)

P.S.
It may help to figure it as an BJT Emitter follower of much larger V_BE and almost infinite h_FE..

[MaxPower]

How about using a pot as the source resistor and adjusting it until you get the desired voltage? Or do you have to muck about with the drain resistance as well?

[antonis]

In case of pot use, it should be better to be used for Gate bias purpose..

[MaxPower]

Gah, the op amp mixer keeps looking better doesn't it?

[antonis]

Sure but it's no fun, isn't it..??

[BuddyPrince]

However, I'm still left with the question, how do I get the source voltage down to 4.5v?  The bias voltage seems to be int he right range...

You have to set it by Drain current and Source resistor value..
(V_S = I_D X R_S..)

Biasing Gate to a given voltage V_G and for a desired quiescent Drain current I_D, you can estimate Source resistance value needed from transfer characteristics curve of your specific MosFet..
(taking in mind that Source voltage V_S should be slightly more than V_TH below V_G..)

e.g. For a desired I_D of 1mA at V_GS of 3V with 4k7 Source resistor, Gate bias voltage should be on 7.7V for a V_S of 4.7V..
(provided  V_TH < 3V..)

P.S.
It may help to figure it as an BJT Emitter follower of much larger V_BE and almost infinite h_FE..

Thanks Antonis!  My next question, how do I determine the desired drain current?  Is it related to the output current of the instrument? Do I need to bias each MOSFET with the appropriate resistor to get V_S to be consistent across each MOSFET?

[MaxPower]

From the datasheet I'm guessing. The specs RG posted for example. Just a guess though.

[antonis]

My next question, how do I determine the desired drain current?

That should be your FIRST question..!!
When designing an amp, either CS or CD(Source follower), we first take in mind output current (load requirements) which current shouldn't be more than quiescent current (steady current due to DC bias..)
e.g. if you bias each of your followers for a 1mA quiescent Drain current (at half the supply voltage), maximum Drain working(total) current shouldn't exceed 2mA..
(actually, Drain quiescent current should be 10-15% greater than maximum Drain current due to signal peaks..)

so,

Is it related to the output current of the instrument?

Yes..!! 
Determine your load current needs and decide for your Drain-Source current..
(which isn't difficult for a Source follower with gain less than unity and Source resistor much lower than load driven..)

Do I need to bias each MOSFET with the appropriate resistor to get V_S to be consistent across each MOSFET?

Of course..!!
(although it took me some time to realize you're talking about Source resistors..)

Each transistor has it's own Source & Output and I'm sure you don't want to mix them up..
Long-tail pair("troika" in your case) doesn't apply to Source followers..
(It might apply to Common Source amps of identical (copy-paste) FETs - more on this written by W. Shakespere "Midsummer Night's Dream", 1595/96..)

P.S.
In case you're talking about only one(common) bias resistor for all three Mosfets,the answer is still YES..!!
(FEts exibit wide parameter spread, even among identical items, so using only one bias source shouldn't work..)

[antonis]

I might confused you a bit so let's face it on paper..

A Source follower exibits a voltage gain of unity (let's keep 0.05 - 0.03 difference as safety margin)..
Biased at 4.5V, it needs a signal peak greater than 4.5V to clip (Voltage DC+AC level up to Supply voltage magnitude)..
As far as our signal peak is lower than the voltage our Source is biased at, we don't have to worry about..

That given, we now have to worry about load current need for maximun voltage swing..
For a load of 47k, say, and a signal Vp of 4.5V, say again, our load "draws" slightly less than 100μA..
That leads to work with Drain quiescent current of 200μA (or more)..
For that current, we need a 22k5 Source resistor to have a quiescent Source voltage of 4.5V..

We know search for V_GS appropriate to give 200μA Drain current..
Let's say that V_GS is 2.3V, for a V_DS of 4.5V..
So, V_G should stand on 4.5+2.3=6.8V..
We need a voltage divider of R1/R2=0.755 (actual values due to PS current consumption availiability..)

Summarizing, we place a 22k5 Source resistor, we set Gate voltage at 6.8V and voila..!! 

P.S.
The above is just a bias rule of thumb with arbitrary taken values..
More close to your case should be to work with 3k3 to 4k7 Source resistor, about 1mA Drain current (more or less) and a trim pot for individul Mosfet V_GS setting but I leave it on you as an implementation task..
(in case of your circuit won't work you'll be able to find the reason(s)..)

[MaxPower]

Holy hell, op amps are cool! Seriously though, those are some great posts (Paul, RG, Antonis).  Lots of great info. My copy of Electronic Principles glosses over Jfets and mosfets.

[BuddyPrince]

Awesome! Thanks guys!  I'm going to work on digesting and implementing these things...

Will update as progress happens...

[BuddyPrince]

Well...I got the JFETs I had wanted from the get go, soldered them in, and got my circuit working.

I deeply deeply appreciate all the knowledge you all have shared with me!  I feel like I have a much stronger understanding of biasing in general, and JFETs and MOSFETs in particular.  No doubt my knowledge is still quite elementary, but it's better than before.

Thanks everyone, in particular R.G., PRR and Antonis!

[antonis]

I got the JFETs I had wanted from the get go, soldered them in, and got my circuit working.

So we've here a great lucky beggar...!! 
(I shouldn't ever dare to dream of a JFET working circuit without socketing & trimming..)

Glad to hear your circuit works, BudduPrince..