Whats the difference with these 2 JFET voltage buffers?

[Boner]

I've been using the first for the longest time, I then came across the second type online somewhere and I have no idea the practical differences.

Does slapping a jfet on the JFETS source like in the second one turn the buffer into a current source? I've been simulating different designs using both and have yet to see any benefits. Of course I'm dumb so maybe I'm missing something.

[Rob Strand]

The lower JFET is a current source.

The current source load gives you maximum gain (ie. closest to one).  It also gives you least distortion.
A lot of HiFi people used the current source load on BJT buffers for this reason.
The reason it does this is because you can set the bias current without loading the buffer.
All this falls away unless the next stage has a high impedance.

[Boner]

The lower JFET is a current source.

The current source load gives you maximum gain (ie. closest to one).  It also gives you least distortion.
A lot of HiFi people used the current source load on BJT buffers for this reason.
The reason it does this is because you can set the bias current without loading the buffer.
All this falls away unless the next stage has a high impedance.

Thank you!

Now forgive me if this sounds dumb, but a jfets drain is "high impedance" and its source is "low impedance", correct? So if I replace a single JFET buffers source resistor with a current source like in the second buffer, the next stages input impedance must be way higher than either the top jfets source impedance or is it the lower JFETS drain impedance?


For example if the next stage is a JFET amp for example, how high should the next stages input impedance be relative to the current source? For example if the current source is a j201, is there a parameter associated (drain impedance?) with the j201 that can give me insite into what hte impedance should be? Or is it generic and on the order of 1M?

[Rob Strand]

the next stages input impedance must be way higher than either the top jfets source impedance or is it the lower JFETS drain impedance?

In this circuit, load is related to the source impedance (the lower one).

For example if the next stage is a JFET amp for example, how high should the next stages input impedance be relative to the current source?

There's no right value as such.   It's all to do with how close you want you gain to be to 1.

Like for the current source load, if the JFET's source impedance was 1k, a 10k load would give you a gain of 0.91 , a 100k load would give you a gain of 0.99 and a 1MEG a gain of 0.999.   There's a point where you have a large choice of impedances which are fine.

There's a couple of things I should point out. 

The higher the source current the lower the JFET's source impedance is.    If you run JFET at 10 times the current the source impedance will reduce by a factor of sqrt(10) = 3.2.

Now I should have been clear about this before.   In order to get 10 times the current with a resistor on the source you need to reduce the resistor value by a factor of 10.   However by doing that the source impedance has only decreases by a factor of 3.2.  So things are worse and the gain is lower.

However, when you use a current source you can increase the bias current independent of the load.   So by running the JFET at 10 times the current  the JFET source impedance decreases by a factor of 3.2.

This is one advantage of the current source load over the resistive source load.

[antonis]

<off-topic on>

Can't see any reason for desperately trying to set as close as unity the gain of a FET buffer..
(at least, other than trying to raise it's - already high - input impedance by bootstrapping..) 

<off-topic off>

P.S.
<Of course I'm dumb so maybe I'm missing something>
@Boner: You might consider yourself dump if you didn't miss anything..!!