Request: Slow Gear Circuit Analysis

[thehallofshields]

There is a lot of discussion around this circuit on the web, but I have yet to come across a formal breakdown / analysis of the circuit.
Myself, I understand about 30% of what is going on, but most of the magic is lost on me.



If someone has some terminology, concepts or articles to share, that would be awesome. If I don't get much of a response, I'll just start firing off some questions and see what happens.

[effexfreek]

oooh-LorDY, YEEEESSSSSSS !


   I second that request, pretty please !

   O.k., First Salvo : it doesn't look like the side-chain is behaving like your "standard" (opamp) comparator now, does it ? It seems it's having some of the actual "effected" signal fed (through R10-C7) to T2 FET's gate (signal-feedthrough nulling, perhaps ?), and some of the "FWR Envelope" (again, nulling ?) fed (through TRim1-R24) to its source... ? drain... ? I couldn't say which.    ...oh, so confused by it all...

   I'm remarkably thick  when it comes to such subtleties, as circuit anlysis. I'd looove the real dirt on this circuit.

   In any case, it looks real clever !


Tag ! Next up !

P.S. : before having mine stolen waaaay back, I'd modified it with a duplicate 1/4" jack/input buffer, wired solely to the "processing" side-chain (having disconnected the actual signal input from said side-chain), to be able to "swell" later in the effects chain (post-fuzz, say), but still having the cleanest (best dynamical) guitar-signal possible, for more reliable/consistent triggering... worked quite well !

[PRR]

Please describe what this thing does or sounds-like.

[blackieNYC]

It's a slow attack thing.  Sound ramps up from nothing like volume pedal swells. Can also
Function as a noise gate. 

[Transmogrifox]

How deep of analysis do you want?

A qualitative analysis is not so much to ask -- this is just somebody giving a description of what each circuit element does and how it all works together as a system.

A quantitative analysis is much more difficult -- this includes mathematical expressions for the gain, deriving closed-form expression for gain vs signal amplitude and even more complex would be expressing the frequency dependence and other complex interactions due to nonlinear elements.  This type of analysis could include effects such as intermodulation distortion due to side-chain ripple.  I'm an experienced analog engineer, but there are things happening in this circuit that would stretch me to my limits to express in a complete, rigorous quantitative form.  I am doubting you want an analysis that goes that deep, and I prefer to reserve that kind of thinking for people who pay my living to think that way.

On the surface this circuit is pretty simple:  Sidechain has a good deal of gain (IC1) and feeds a full-wave rectifier (T5,T6), which is filtered by C15 and C6.  \

The weirdness around C16, R24, C4 helps preserve small-signal linearity on the FET by dynamically adjusting the bias.

The part of the signal chain that is interesting to follow with your eyes is the connections from T5,T6 collectors to the gate of T2 (FET) gate.  The filtered full-wave rectifier pulls down on the FET gate, shutting it off.

As the FET shuts off, it acts a large-value resistor to virtual ground, and by this means turns the signal level up as you dig in.

Another layer deeper analysis could involve a simulation in which the nonlinear transfer function is plotted vs input signal level.  I'm guessing it will be a quadratic (x^2) type of function...but because of the timing on the RC filter there will be an exponential relationship in there due to the time domain response of the rectifier and attack control.

(e^x)^2 = e^2x, which is just a time constant change in the exponential function...but this is an over-simplification.

T1,T3 are just input and output buffers.  C3, C5 are DC blocking caps.  \
R10, C7 linearize the FET as a resistor, reducing distortion somewhat.

[R.G.]

It's an attack-delay circuit. The attack of notes is cut off and the note ramps up a bit at the start. It's an attempt at a live "reversed tape" sound.

T1 and T3 are buffers to take any loading effects off the inside works.

R4, R6 and T2 are a voltage divider operating on the buffered signal.

T2's source is held up at 5.6V by the zener and resistor. It's gate normally floats at about the same 5.6V, pulled there by R7 raising the voltage on C6.  Pulling the gate below this voltage progressively turns T2 off.

So normally, little if any signal gets through. It's a kind of noise gate in the sense that will small signals, it's almost muted.

When a bigger signal comes through, it is amplified by IC1, phase split by T4, and effectively FWR'd by T5 and T6, the circuit being very much like the rectifier/envelope circuit in a Dynacomp. This one pulls down on the gate of T2 through the attack control acting on C6. It's not instantaneous, as it takes some time for it to pull C6 down with the attack control limiting how fast C6 can discharge.
The setting of the attack control sets how fast the T2 FET can be turned off; turning off, remember, equals letting the signal through nearly un-attenuated.

So it nips off the start of a note, and ramps up to letting the note through. When it's quiet between notes, the FWR quits pulling down on C6, and it resets to "gated off" and waits for the next bigger signal pulse.

No biggie.

[thehallofshields]

oooh-LorDY, YEEEESSSSSSS !


   I second that request, pretty please !

This guy says what I'm thinking inside.

How deep of analysis do you want?

What you gave was pretty good! These "The Technology of the X" articles that people do are very popular.

On the surface this circuit is pretty simple:  Sidechain has a good deal of gain (IC1) and feeds a full-wave rectifier (T5,T6), which is filtered by C15 and C6.

So the side-chain is just a FWR?

- IC1: Amplifier
- T4: Phase Splitter
- T5/T6: Match / Balance Impedance from the Phase Splitter

I don't get it, why not just us Op-Amp Precision Rectifier?

[thehallofshields]

Here is my crude understanding so far.

[thehallofshields]

The C7 - R10 components are confusing the hell out of me.
The FWR signal is already being fed into T2 Gate, why drizzle some of that to the output?



It's not like you're going to get noise-cancellation or anything out of that.

[effexfreek]

Transmogrifox from reply #4 :

"R10, C7 linearize the FET as a resistor, reducing distortion somewhat.."


   ...by letting the FET get half the "effect" signal (R10/1M-C7), half the control voltage (1M) ?!


MIND.   BLOWN.

[thehallofshields]

Transmogrifox from reply #4 :

"R10, C7 linearize the FET as a resistor, reducing distortion somewhat.."    ...by letting the FET get half the "effect" signal (R10/1M-C7), half the control voltage (1M) ?!


MIND.   BLOWN.

So I had it backwards? The output is being fed back into the FET Gate?
And rather than noise at the output, we get stability at T2 because... though the CV is much hotter (higher amplitude), the output of T3 has much lower Impedance?

*scratches head*

[R.G.]

JFETs have issues with causing distortion when used as a variable resistor and the signal flowing across them is too big. This is because the gate is not an actual point, but is spread across the entire length of the channel from drain to source. If there is much voltage in the drain to source channel, it actually modulates the gate to source voltage, and hence modulates the channel resistance too.

This can be tamed downs some by applying feedback from drain to gate of about half the signal. In the schematic, C6 and C7 may termporarily be thought of as DC open circuits, and AC signal short circuits. The signal at the drain of the JFET-used-as-a-variable-resistor is buffered by T3, so we can think of the signal at the emitter of T3 as almost exactly the signal at the drain of the JFET. R10 and R8 divide this in half (C7 and C6 are signal short circuits, remember) and applies half of this to the gate. This mostly cancels the internal gate-riding-the-channel effect inside the JFET, and makes the JFET act like a variable resistor up to a couple of volts across it.

Without the half-feedback, the distortion gets bad at much smaller voltages. The only penalty to pay is that the control voltage signal - the DC signal fed between the gate and source - now has to be about twice as big. So you get much less distortion in return for halving the sensitivity of the JFET to a control voltage. It's a good trade to make.

As the originator of the "The Technology of..." articles, it makes me happy that others are trying to carry this on to teach other people about how circuits work.

[effexfreek]

aaahhH, yes... !


...I remember now, having seen (while intensely searching the net about conpressors) this "trick" used & explained, 'though usually, the signal is taken directly from the drain (in compressor feedback topology I've seen). THAT's what threw me off !  ...well, among other things lotsa things... 

   As an eager reader of all your "The Technology of..." articles, it makes me proud to thank you for all the hare-brained plans you inadvertently contributed to hatch in my mind, and henceforth, the countless hours "wasted" daydreaming of "impossible effects to come" ! 


Thanks R.G. & Transmogrifox,
I salute you both


...oh, AND thehallofshields as well, as I didn't have the balls to ask in the first place !

[effexfreek]

I suggest, maybe renaming this thread : "Circuit Analysis : The Technology of Slow Gear" ...? 

[BluffChill]

Has anyone successfully breadboarded one of these? Of all the schematics I've seen, there has always been doubt cast on it or the diagram is incomplete, or with questionable component values. Would be interested to see if there's a verified vero out there somewhere.

[effexfreek]

MAN ! I just remembered I had an original SG-1 Service Notes (with schem.)  here's what's different (original) from THIS schem :


C1=100n
R2=220k
C6=680n  -->about node C6-R7-R8-20kbAttack pot :

   In the original, (*what I'm guessing is*) the "ON" side collector of the BOSS flipflop circuit drives the base of a 2SC1815 (like a BC549 in this schem.) through a 470k, its emitter (arrow side) connects to both emitters of the flipflop (all grounded through a 1S2473 diode ; probably a 1N4148) and FINALLY, the 2SC1815 collector connect to the C6-R7-R8-20kbAttack pot node through a 1k resistor... maybe THAT'S the culprit ? You would want to "simulate" (*what I think is*) the "ON" condition of the 2SC1815 for that node (that is : if you won't be using the standard BOSS flipflop & doing true-bypass)... ? (or is it the other way 'round ? "OFF" ?)

Sorry if this is confusing    I'm confused


Aside what I've noted up here, everything else looks the same... hope that helps !

[PRR]

> why drizzle some of that to the output?

Not even "drizzle".

On the face of it, 1Meg feeding 10K can only come through at 1% strength.

If you can quickly rough-estimate a transistor, this emitter follows its base with maybe 100 Ohms impedance, so the "drizzle" is like 0.01%. Can't hear that.

So if that's not it, what is? How about this 1Meg and the other 1Meg make a mixed signal to the gate. It would! But why?

When we put real DC on a JFET we call one end the source and we look at gate-source voltage to think what it will do.

But the source and drain are 99%-100% identical. When we have no, or very-low, "gate voltage", which end do we measure to? And one way or the other, small AC signal source-drain will cause some upset to the effective gate voltage.

What we really want to do is reference to the *center* of the JFET channel, the average of source and drain (or drain and source). That minimizes trouble (which appears as distortion).

[Transmogrifox]

So the side-chain is just a FWR?

- IC1: Amplifier
- T4: Phase Splitter
- T5/T6: Match / Balance Impedance from the Phase Splitter

T5/T6 are a pair of 1/2 wave rectifiers working off the phase splitter--not really an impedance matching thing.

I don't get it, why not just us Op-Amp Precision Rectifier?

That would be a valid approach.  I can make guesses as to why the original designer did it with transistors instead of op amps, but whatever the reasons, he found a way that worked well...and did it.

[duck_arse]

I've always wondered about the function of R19/C12. why do we want spikes driving the transistor?

[thehallofshields]

Has anyone successfully breadboarded one of these? Of all the schematics I've seen, there has always been doubt cast on it or the diagram is incomplete, or with questionable component values. Would be interested to see if there's a verified vero out there somewhere.

From what I gather, it's a finnicky circuit. Quite a lot of people who buy PCB's for these from BYOC and GGG have complained they can't get it working after multiple builds.

Never built it myself though.