Selecting JFETs for preamp pedals

Started by Scribe, March 18, 2019, 01:47:04 PM

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Scribe

Hey all,
I've been recently reading up on JFET preamps lately and recently bought my first batch of j201s to play around with. I'm interested in experimenting with the Feztzer Valve and Mu amp setups to try some different projects (BSIAB, Model T FET preamp, etc). There seem to be a few different methods for testing which JFETs work well in these circuits, and was wondering if those of you with a bit more experience would be willing to answer a couple questions:

1) What is your preferred method for testing your JFETs (Idss, Vg, etc)?
2) What range of values do you consider 'good' for the Fetzer/Mu amp stages?

Thanks as always!
Matt

GibsonGM

Welcome, Scribe.   Why don't you check this out?  You didn't mention if you'd found this page yet...it is pretty descriptive re. what's going on.
http://www.runoffgroove.com/fetzervalve.html

I've been using the following method to measure Idss, Vgs off, it was discussed in the forum a while back as a nice, quick & dirty way to get them. 

Plug your values into the calculator on the page above, and see if the numbers work out!  ;)  Someone more into FET characteristics will come along and describe more why some FETs have more preferable ranges than others, having to do with signal swing and ability to amplify.

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antonis

#2
Could you elaborate more of your wonderful sketch, Sir..??  :icon_redface:
(some of us haven't delve deeply into minimalistic abstract art..)
"I'm getting older while being taught all the time" Solon the Athenian..
"I don't mind  being taught all the time but I do mind a lot getting old" Antonis the Thessalonian..

GibsonGM

#3
It is not my sketch, Antonis.  I stole it  :)     It has a name on the bottom, so I assume they are OK with re-posting.

If one follows the schematic instructions, in the first example, you set up the JFET with gate grounded, drain connected to +9v, and measure voltage between source and ground.  Vgs (off) is the gate to source voltage at which drain current becomes zero because of the spreading of depletion layer, which in turn reduces the length of conduction channel. The numerical value of both pinch off and Vgs (off) is the same.


In the 2nd drawing, gate and source are grounded, and a milli-Ammeter is set up between the drain and +9V.  This will return (in uA) the approximate IDss IDss.  (referred to as the drain current for zero bias), which is the maximum current that flows through a FET transistor, which is when the gate voltage, VG, supplied to the FET is 0V. 

These values are used in the calculator found at Runoffgroove that I linked to above the pic, to find the resistors needed for optimal biasing of your particular JFET.  The formulae used are also there, in case you'd like to learn more about the math behind the operation.    The numbers this simple method uses are not exact, but they are generally close enough for the work we're doing here!

HTH

~MP
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antonis

I was teasing you before Mike  :icon_redface: but now things get serious.. :icon_eek:

Quote from: GibsonGM on March 19, 2019, 09:09:17 AM
IDss (referred to as the drain current for zero bias), which is the maximum current that flows through a FET transistor, which is when the gate voltage, VG, supplied to the FET is 0V.
Plz allow me to inform your Highness that maximun current usually occurs when the Gate voltage is slightly possitive in relation to Source..(also depended on Drain to Source voltage..)    :icon_wink:
(commonly used configuration for DC full-on purpose for a theoretical zero channel resistance..)

P.S.
Temperature enviroment difference of 230C minus X(*) isn't convenient for a healthy argument, is it..??
(*) where "X" place your local temperature, in Celcious degrees if possible.. :icon_wink:
"I'm getting older while being taught all the time" Solon the Athenian..
"I don't mind  being taught all the time but I do mind a lot getting old" Antonis the Thessalonian..

GibsonGM

Quote from: antonis on March 19, 2019, 10:38:06 AM
I was teasing you before Mike  :icon_redface: but now things get serious.. :icon_eek:

Quote from: GibsonGM on March 19, 2019, 09:09:17 AM
IDss (referred to as the drain current for zero bias), which is the maximum current that flows through a FET transistor, which is when the gate voltage, VG, supplied to the FET is 0V.
Plz allow me to inform your Highness that maximun current usually occurs when the Gate voltage is slightly possitive in relation to Source..(also depended on Drain to Source voltage..)    :icon_wink:
(commonly used configuration for DC full-on purpose for a theoretical zero channel resistance..)



Yes, absolutely...I stole that definition from a web page that was dealing in 'fast and dirty' calculation, just as we are right here!!!  :)   To an approximation, it will be "good enough".   I have not had any problem using this method yet, at least!



--------------------------------------------------------------------------------------------------------------
OT:   My local temperature is -11C.  :)  That tells me it is really VERY, VERY close to SPRING TIME!  It is warming right up!

Here is the snow outside a room in my home that I just restored.  I hope the snow and ice do not break the new windows.  That was taken about 3 days ago.

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antonis

#6
 :icon_eek: :icon_eek: :icon_eek: :icon_eek: :icon_eek: :icon_eek:

Ideal place for absolutely zero Gate leakage current...!!!  :icon_wink:
(you could bias your FETs with a 100MΩ resistor with no problem at all..)
"I'm getting older while being taught all the time" Solon the Athenian..
"I don't mind  being taught all the time but I do mind a lot getting old" Antonis the Thessalonian..

GibsonGM

It does not get down as low as 0K, but at times one might believe it was close! 
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Scribe

Thanks for the posts and clarification - the ROG article is very useful. My one remaining question is after measuring multiple JFETs, which ones are ideal for use in gain stages?

I hear lots of people over the forum talking sorting JFETs by their Idss to find ones that work best for gain circuits. Some stages use trim pots to compensate for some variability, but others (like the Mu amp) don't.

I'm guessing its  important to select JFETs with an Idss within a certain range, but what is the selection criteria?

GibsonGM

To the best of my understanding, which JFET to choose is mostly based on compromise...you will have to tweak components to optimize your circuit to deliver the best signal reproduction and gain.  Some are chosen because they have more gain available, good ratio of gain to noise...some are better than others (J201 higher gain than 2N5457).   It depends where in a circuit they're used - in 1 case, having max. gain may be critical to the performance of the circuit.   In another, such as a generic booster, it may not matter as much.   
This is why we have to match them for use in phase pedals, but don't for distortion/preamp type things.  Like anything - if something downstream depends on a certain level of signal being present, then you will have to play around / experiment with different devices.

http://diy.smallbearelec.com/HowTos/BreadboardBareAss/BreadboardBareAss.htm

http://sound.whsites.net/articles/fet-applications.htm
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Eb7+9

#10
Quote from: antonis on March 19, 2019, 10:38:06 AM
Plz allow me to inform your Highness that maximun current usually occurs when the Gate voltage is slightly possitive in relation to Source..(also depended on Drain to Source voltage..)   

Funny how peeps in this forum go off topic to try to sound right about something (else)

The scribbles I drew were meant for those who can see forest for the trees

The idea of a max jFet current is of course done in the context of transistor operation
When Vgs goes above zero the jFet device degenerates into a diode, ie transistor action is lost

So max current when device operating as a transistor ... is correct context

—-

Back to op q’s

The choice of Vgs(off) values will determine max input referred headroom

This applies to mu stages where voltage gets converted to current
ie,. bottom device ... same as single device common source jFet gain stages

In other words pick Vgs(off) to be at least as large as desired input headroom
If you want to build clean sounding gain stages

If you’re using mu stages to create dirt you want low Vgs(off) devices
hence why the J201 sounds great in the BSIAB for example

here’s something pseudo scientific for you to try:

measure approx value of Vgs(off) using technique shown above
Order all your devices in terms of Vgs(off) estimates

Take four lowest and four highest value devices

Build a BSIAB (two cascaded mu stages if I recall) with two lowest value devices in the bottom position ...
and then with two higher in the top position

Then try doing the reverse:
Two highest Vgs(off) value devices in bottom slots
and two lower ones in top slots

Then use four lows and then four highs ...

See if any conclusions can be derived ...
(dirt characteristics versus gain n knob settings, etc)

good luck


PRR

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