Debugging Wampler Black '65 - very quiet and clean

[steffen]

Hi everyone, I am having issues with this project:
http://tagboardeffects.blogspot.com/2012/08/wampler-black-65.html
from IVIark's blog. I am using a vero board and followed the layout on the blog as closely as possible, without any mods. The only things that differ from the schematic are:
- 2x 1uF caps in the schematic are not polarized, whereas I used polarized ones and connected the positive lead to the drain in both cases
- in place of the 2x 10pF caps I used 100pF caps, which is according to comments what was actually used in the original pedal.

I used J201 JFETs (as per BOM) bought at a German online shop called Banzai Music (I live in Europe) and used 50k trimmers for biasing the JFETs.







Here are the voltage readings:

Battery:
V+: 8.24
V-: 0

Q1
D=4.47
S=0.03
G=0

Q2
D=4.42
S=0.11
G=0

Q3
D=4.47
S=0.22
G=0

Q4
D=4.42
S=0.11
G=0


The problem I have is that the pedal is very quiet and the effect on the signal is barely audible, in both positions of the boost switch (although when boost mode is on, the signal is slightly louder and dirtier).

My debugging setup consists of an audio probe connected to an Apogee Jam 96k  audio interface on my Macbook which is running SignalScope Pro.
SignalScope is generating a sine wave at 1Khz with 328 mV peak, 231 mV rms and displays the input signal from the audio probe on an oscilloscope.

I traced the signal path using the audio probe and there seems to be a problem around Q3 where the signal comes in at the G pin at 1.3V peak, 928mV rms and comes out of the D pin at 466 mV peak, 369 mV so there is almost a 3x attenuation.

Here are some screenshots of the oscilloscope showing the traced signal at different points in the circuit. The following is with both gain and volume maxed out and boost switch in on position.


generated signal directly connected to input of Apogee Jam 96k (1Khz):


taken at pin G of Q1:


taken at pin D of Q1:


taken at pin G of Q2:


taken at pin D of Q2:


taken at pin G of Q3:


taken at pin D of Q3:


taken at pin G of Q4:


taken at pin D of Q4:


I did check the readings at the electrolytic caps and verified that the voltage on the positive lead is more positive than the one on the negative lead.
I searched the forum and noticed that some other people had problems with this circuit, however none of them seems to have had this particular issue and their pedals worked fine once they managed to bias the JFETs with the desired voltage (4.5V to 5V range). However, this didn't do the trick for me and any help would be highly appreciated.

[Kipper4]

Show us the schematic your comparing it to please.

[steffen]

sure thing @Kipper4

[steffen]

I tried bypassing everything in between Q3 and Q4 (included) by disconnecting Q3's drain pin from the socket and running a jumper wire from Q3's drain to the socket pin where Q4's drain pin normally goes. With this setup the signal at Q3 does not attenuate but rather has a 2x gain, so I am guess the problem lies somewhere in between Q3 and Q4 but I can't figure out what that is, for the life of me. Please help! 

[mth5044]

Have you tried audio probing the components between Q3 and Q4? Have you tried swapping Q3 with other transistors to see if it's a part issue? Triple check all of your parts in that area.

[steffen]

Thanks for your input @mth5044
the problem is that when Q3 is connected normally (according to the schematic, that is) the signal gets attenuated right at the drain, so audio probing the components down the signal path between Q3 and Q4 doesn't really help me, or maybe I am missing something?
I also tried swapping Q3 with other J201s but the behavior is identical.
What would you recommend I check? I don't have a lot of experience...   

[reddesert]

The gain of each JFET stage depends on the value of the drain resistor: gain = Rdrain / Rsource. You're using trimpots to adjust the drain voltage to a desired bias point, which is reasonable but also means that the gain of each stage depends on where the trimpot is set. JFETs are highly variable in manufacture, so your JFETs are likely different from Wampler's, and you might find that the circuit doesn't sound the same. You can try measuring the resistance that each trimpot is set at to see if that explains why stage 3 might be low gain. If that is not a plausible explanation, then keep looking. If it is plausible, then you can try adjusting the trimpot, offsetting the bias of the stage, to see if you like the sound better. Biasing them at +4.5V is just a guideline, not a firm rule.

(I have built this circuit and mine does not attenuate the signal, but I think it is cleaner / lower gain than Wampler's original.)

[steffen]

Thanks a lot for your input @reddesert.
I did another test and disconnected the part of the circuit that follows Q3's pin in the signal path. With this setup, the signal at Q3's drain looks and sounds good, which would indicate that the biasing of Q3 is ok. However, as soon as I connect Q3's drain pin to the subsequent circuit section (the tone stack) the signal attenuates, which, again indicates something wrong around that area.
I have now ordered one of those cheap Chinese component testers which I found being mentioned around in this forum and will see if that sheds any light.
By the way, could I use that tester to check the J201s? and possibly select the best among a batch of them for this project?

[reddesert]

If the signal is dropping a lot when the tone stack is attached, then I would look for either a short or an incorrect component value in the tone stack, that is shunting too much of the signal to ground.

I use a knife to slice between each of the horizontal rows of a veroboard after doing all the soldering. This can cut or displace short circuits from leftover traces of solder, some of which are too inconspicuous to see by eye.

I have one of those cheap component testers, and they're fine, but they're better for testing components out of the circuit. In a circuit, a DVM or component tester can sometimes be fooled by other components wired in parallel with the part under test. Check all the labeled values of components again. The labeled values are almost never wrong, but sometimes it's really hard to tell red from orange on a resistor, etc.

[steffen]

I was planning to unsolder all the parts in the suspicious area, test them and then reassemble that circuit segment on a breadboard in order to rule out issues introduced by bad soldering/veroboard short circuits and facilitate pinpointing the issue, but yeah, your suggestions make a lot of sense - thanks a lot!

[Kipper4]

You will always get some insertion loss after a tone stack. So a weak signal is expected after Q3.
That's why theres a gain stage after the stack to make up for insertion losses.

Also note that all 4 fets are biased the same. Rdrain 5k6     Rsource 1k

What your voltages now? Q1-4
'Cause if all fets are biased the same they should all be similar no?

If signal is good at Q3 drain then start looking at Q4 and double check the tonestack connections.

Happy hunting
Kipper

[steffen]

@Kipper4 I will do as you say.
One question though, and I realize I may sound very ignorant here, but is the signal loss expected right after Q3 (before the tone stack segment) or after the tone stack itself? I can wrap my head around the idea of a signal loss after the tone stack, but how is the signal loss justified right after Q3, and only when connected to the tone stack, whereas there is no loss when the signal path is cut open at that point?

[Kipper4]

Loss after tone stack. Sorry busy and at work now

[idy]

Tone stack will cut volume, they do that... But if there is a problem, like a short or too-small resistor to ground, the volume drop may appear right after the transistor. Sometimes the problem appears at the "entrance" of the "problem" component or area. If disconnecting the tone stack gets rid of the problem, I think we both know where the problem is...

[Jeema]

Check your Q3 source and drain resistor values. You probably have a 10k instead of a 1k or something like that.

[steffen]

@Jeema I did check that and the resistor values are correct.

While I wait for the component tester, I have a few questions that hopefully some of you can help me with (thanks for all the help so far everybody).

The drain resistor values I currently have at the trimmers are in the range 19K - 81K.
If the gain is determined by the ratio Rdrain / Rsource and Rsource is always 1K, does it mean I should have 19x to 81x gain across my circuit? Looking at the oscilloscope readings it doesn't look that way though, and I am quite puzzled.

Someone on this thread (http://tagboardeffects.blogspot.com/2012/08/wampler-black-65.html) recommends tweaking the source resistor values as well. Why is that?

Also, I am reading a lot about fake J201s being shipped lately, which seems to be a consequence of the scarcity of such components. I am wondering whether the problems I am having are related to bad J201s. Does it make sense I get some of the (apparently) more reliable and consistent SMD J201s with an adapter?

[steffen]

So the component tester arrived and all parts between Q3 and Q4 are reported as healthy and with correct values. The only strange thing is that the tester reports all J201 I have as two diodes with ~1V forward current. Not sure whether it's because they're all faulty or because the tester is wrong, but according to specs it should be able to test JFETs fine.

Having unsoldered all components between Q3 and Q4 I also took the chance and connected them on a breadboard, to rule out problems with the veroboard strips like short circuits or soldering issues. However, I observe the same exact behavior as before.

In this forum thread (http://freestompboxes.org/viewtopic.php?f=7&t=16177&hilit=black+65&sid=56284c5a747eb908b42b11791e105c2f&start=40#p209774) a guy mentions that the signal in this circuit is supposed to stay at 8V peak-to-peak, which differs a lot from what I have here.

The only other thing I can think of trying while I wait for the new J201s SMD I ordered ( ) is tweaking the source resistor values, but I'd rather wait for someone to chip in and shed light about the questions in my previous post.

[mth5044]

If you're going to start tweeting the source resistors, might be worth while using the ROG calculator and trying the source and drain values it recommends

http://www.runoffgroove.com/fetzervalve.html

[Kipper4]

I've just noticed the part about you using 50k pots to bias the fets.
While the schematic shows a value closer to 5k (5k6)

[PRR]

> If the gain is determined by the ratio Rdrain / Rsource and Rsource is always 1K, does it mean I should have 19x to 81x gain

The FET's internal resistance, "roughly 1K" is in series with Rsource; gain is typically "half" what the formula says.

Whatever the load is is in parallel with Rdrain. For the original values of 5.6k and 100k-500k, this is a small effect. If you have "had" to push Rsource much higher to get a happy DC point, say 81k, then 100k across that cuts gain nearly in half.

The FET also has an internal source resistance, shunt to load, which limits gain.

IMHO, if you do not have same-batch as the Designer's FETs, it may be best to leave Rdrain at stock or roughly mid-way on a trim, then fiddle Rsource to find a happy DC point. Rdrain really should be about a good fit to the Load. Rsource is less constrained. However if you are using very different FETs than the original, no patch-up can get the same result as the original.