Messing about with the CD4046 VCO and other stuff.

[anotherjim]

I'm strangely fascinated by this chip, despite its imperfections in its intended role as a phase-locked loop (pll). I think it might be a little more versatile.
The chip contains 2 parts. There is the VCO (which internally is a current controlled oscillator) and a bunch of logic that provides the phase comparator for pll operation.
Starting with the VCO section...

This is simpler than it looks.
With the inhibit input low, current can flow down via the top Pmos P3.
P1 and P2 are a current mirror. A control current down via P1 is mirrored into the oscillator timing path. The control current is set by those external resistors R1 and R2 and the action of N1 according to the pin9 control voltage.
The oscillator action is based on Gate 1 and 2 forming an RS flip-flop and those complentary pairs P4, N2 and P5, N3. One Nmos will hold one side of the timing cap C1 at 0v while the Pmos at the other side lets in the control current from P2. The current and the size of the cap cause a linear ramp voltage to rise until the logic level forces the flip flop to change state. The charged end of the cap is forced to 0v by its Nmos and now the opposite side of the cap charges up.

The yellow trace is one end of the timing cap (either pin 6 or 7) with the blue trace showing the VCO output from pin4.
Clearly, this is an odd waveform  - a very broken sawtooth. A sawtooth is a very useful waveform, and I want a proper one!
Like this...

This is actually 2 waves from each cap pin 6 and 7. All that's needed is a 50/50 mix/blend of these to produce a complete sawtooth albeit at twice the frequency of the pin4 square wave.
Notice that the negative-going "blip" of the original trace at the start of the ramp has been fixed. That occurs when the positively charged end of the cap is forced to 0v, the other end wants to go negative but is clamped in the chip by diodes (not shown in the internal circuit). However, the diodes only limit the negative part to -0.7v. They don't eliminate it.
The circuit tricks to achieve this will be discussed in the next post!
But here's a schematic...

[ElectricDruid]

Thanks very much for that, Jim. Very interesting to see inside that chip a bit more. I've often felt I should be able to do more with it than I ever really managed, so more information helps.

If you wanted a ramp at the same frequency as the square you've got, you could mix your two part-ramps in a proper mixer and then add a bit of the square wave in as well. The square shifts alternate ramps up and down and makes one big ramp instead of two little ramps! Like this:

[bluebunny]

Dunno if you may have seen this, Jim: Thomas Henry's X-4046 VCO Project.  I found it an interesting read.  Might be useful?

[diffeq]

I've seen this diagram in "designing with PLL" document from TI some months ago. What I wanted to try to get a proper saw wave, is break off pin7-cap connection, tie that end of the cap to the ground and tie pin 7 either high or low (through resistor). Then cap ramps up through current source and gets discharged to ground by n2. Single-ended discharge should be glitch-free, in theory. How they use it here is kind of AC-coupling.

[anotherjim]

I've seen this diagram in "designing with PLL" document from TI some months ago. What I wanted to try to get a proper saw wave, is break off pin7-cap connection, tie that end of the cap to the ground and tie pin 7 either high or low (through resistor). Then cap ramps up through current source and gets discharged to ground by n2. Single-ended discharge should be glitch-free, in theory. How they use it here is kind of AC-coupling.

Yes, you'd think that would work. What happens is that the instant "ramp" the logic sees at the no-cap end means that the cap on the other pin doesn't get time to be discharged and the oscillator stalls. There has to be some capacitance on both cap pins. You have seen through to something I'm coming to later!

x4046 project VCO is definitely an influence on my understanding.

The internal VCO diagram is from an applications note. Those functional diagrams are not always complete.

Tom shows how to use the waves (and then a triangle isn't far away and then a sine), however, I'm going to keep the circuitry limited to close to the 4046 itself.



Some key points are...
There are now 2 timing caps to ground instead of a single one between the pins.

The frequency control is by the R2 connection. The normal pin9 and R1 control is unused. Check in the internal diagram to see that pins 9 and 11 are isolated in a way that lets pin9 be the input solely for the pin10 source follower gate if you want. I've tied pin11 to 9 in the schematic. Incidentally, the MOSFET's in this chip are feeble and that 100k source load on pin10 is a good size for it.

So, anyway, the pair of timing caps to 0v eliminate the negative spikes with the single cap. For a 50% duty square wave out of pin4 they must be well matched.
If all that you do is fit 2 caps, this is what the pin 6 or 7 waveform can look like.

The ramp is intact, the negative dip is gone, but why is the return so slow when we want a vertical edge? I think the reason is that with the change to cap connection, the internal Nmos hasn't got the muscle to rapidly discharge the cap.
The solution I've used is to add a couple of cheap BJT transistors to discharge the cap according to the phase of pin4 square wave. A complimentary drive is needed so the BJT's are on for the correct half cycle so the XOR phase comparator that exists between pins 3,14 and 2 is used as an inverter. This last trick is well known from that x4046 although for a different purpose.

Now it looks like this...

[diffeq]

I've seen this diagram in "designing with PLL" document from TI some months ago. What I wanted to try to get a proper saw wave, is break off pin7-cap connection, tie that end of the cap to the ground and tie pin 7 either high or low (through resistor). Then cap ramps up through current source and gets discharged to ground by n2. Single-ended discharge should be glitch-free, in theory. How they use it here is kind of AC-coupling.

Yes, you'd think that would work. What happens is that the instant "ramp" the logic sees at the no-cap end means that the cap on the other pin doesn't get time to be discharged and the oscillator stalls. There has to be some capacitance on both cap pins. You have seen through to something I'm coming to later!

Indeed, since downstream is a flip-flop that relies on either side changing state. Idea: use VCO-OUT and inverters from NAND CD4093 (or CD40106 inverter) to extend pulse for a fraction of uS, to keep pin 7 in the 'opposite' state so that gate has enough time to discharge the capacitor. Of course, this will limit upper frequency somewhat. Remaining NAND gates would allow some 'octave mix' connection. 

BJT idea is cool, never would've thought of that. And it gives both half- and full frequency sawtooth.

[anotherjim]

In original single cap working and if you don't care about the waveforms, the oscillator can carry on working as the frequency rises. Cap discharge toward 0v becomes incomplete but the peak to peak of the timing ramp can get very small before it stops square waves coming out of pin4. At high frequency, the reduction in ramp amplitude is no good if you want that waveform. Plus, control linearity is harmed by the fact that it isn't only the control current determining the ramp time. You may notice I took scope pictures at a reasonably high frequency. At low frequency, the waves aren't so bad without the BJT assistance.
I also tried using gate output to directly pull down the caps to 0v. This has to be via a blocking diode so it can only pull down.

You can see that the inverters can't pull "hard" down to 0v and the diode Vf means there is always a "foot" remaining at the bottom. That was using 4049UB inverters which have one of the best current sinks in the 4000 series. I tried using pin4 and 2 directly and that was better than nothing but still not as good as the 4049. Schottky blocking diodes improve things some more, but nothing really beats the BJT for cost v effectiveness.

Anyway, the next development is to get a full saw from just one cap pin...

From what has already been discussed, I bet you can guess what's going on here.

[diffeq]

In original single cap working and if you don't care about the waveforms, the oscillator can carry on working as the frequency rises. Cap discharge toward 0v becomes incomplete but the peak to peak of the timing ramp can get very small before it stops square waves coming out of pin4. At high frequency, the reduction in ramp amplitude is no good if you want that waveform. Plus, control linearity is harmed by the fact that it isn't only the control current determining the ramp time. You may notice I took scope pictures at a reasonably high frequency. At low frequency, the waves aren't so bad without the BJT assistance.
I also tried using gate output to directly pull down the caps to 0v. This has to be via a blocking diode so it can only pull down.

You can see that the inverters can't pull "hard" down to 0v and the diode Vf means there is always a "foot" remaining at the bottom. That was using 4049UB inverters which have one of the best current sinks in the 4000 series. I tried using pin4 and 2 directly and that was better than nothing but still not as good as the 4049. Schottky blocking diodes improve things some more, but nothing really beats the BJT for cost v effectiveness.

Anyway, the next development is to get a full saw from just one cap pin...

From what has already been discussed, I bet you can guess what's going on here.

I see ramp is 1.2V (two diodes) above ground, so a BJT+diode or BJT+BJT cascade is prolly in there somewhere. VCO-OUT (or is it phase comparator?) output is one diode drop below previous examples, so it goes through that (mentioned in your post). It also lags behind ramp discharge. Hmm.

Maybe these gates have somewhat high internal resistance. Even 2N7000 is around few ohms. Die size affecting it, perhaps. 

[anotherjim]

The raised base level of the full saw is due to the off-time not being long enough for discharge - notice the frequency. That said, I see all sorts of evidence that the on resistance of the 4046 transistors is high and that varies between brands too.
Last pic needs to be seen in connection with a schematic...

In this snippet, going for a full saw from one cap pin needs a small capacitor on pin7 and the main timing cap on pin6. Only one BJT is needed to assist discharge. If pin6 is chosen, then the VCO output from pin4 is the correct phase to drive the BJT and no additional inverter is needed. The cap on pin7 has to be sized to suit the maximum frequency you want for the Sawtooth to keep full amplitude at.
This also shows the pin10 source follower used to buffer the cap wave. It isn't perfect because the Nmos used has some +Vgs to get over, but it can still be useful.
The pin4 output is now a narrow pulse. To get a square, or any duty cycle, the Xor comparator can again be used to process the Saw and this makes PWM possible.

Next, it will be time to discuss the phase comparator logic in the chip.

[diffeq]

The raised base level of the full saw is due to the off-time not being long enough for discharge - notice the frequency. That said, I see all sorts of evidence that the on resistance of the 4046 transistors is high and that varies between brands too.
Last pic needs to be seen in connection with a schematic...

In this snippet, going for a full saw from one cap pin needs a small capacitor on pin7 and the main timing cap on pin6. Only one BJT is needed to assist discharge. If pin6 is chosen, then the VCO output from pin4 is the correct phase to drive the BJT and no additional inverter is needed. The cap on pin7 has to be sized to suit the maximum frequency you want for the Sawtooth to keep full amplitude at.
This also shows the pin10 source follower used to buffer the cap wave. It isn't perfect because the Nmos used has some +Vgs to get over, but it can still be useful.
The pin4 output is now a narrow pulse. To get a square, or any duty cycle, the Xor comparator can again be used to process the Saw and this makes PWM possible.

Next, it will be time to discuss the phase comparator logic in the chip.

Cool. Pulse is enough for a ripple counter to get divisions with 50% duty cycle. Also, comparator can be fed envelope for amplitude-dependant duty cycle change.

[anotherjim]

There is quite a lot in the chips Phase Comparator section. Shame not to use it for other things if it isn't wanted for its intended role in a phase locked loop.

Pin14, the "signal input" has a special input circuit. The "shorted" inverter is the same deal as we know from using CMOS inverters as amplifiers. The feedback around the inverter forces it to sit at half of the supply voltage. In the chip, the complementary pair each have thin channels with high on-resistance as they only need to act as a voltage divider. This and the gain from the following inverters can bring a relatively weak input signal, ac coupled if you want, into the internal logic. Sadly, it is not sensitive enough to work directly off a guitar input.

Pin3 is ordinary logic level.  It is buffered by 2 inverters.

The above 2 pins are the only inputs to this section. The Inhibit to pin5 only applies to the VCO section.

The Phase Comparator I, outputting on pin2, is an Exclusive OR gate (Xor). This only outputs a High level if the 2 inputs have different logic levels, so it really does do a comparison. It can be used like any 2 input Xor can be. If one input is wired high, its an inverter. If one input is wired low, a non-inverting buffer which with a couple of resistors can be a Schmitt trigger.

Phase comparator II is much more complicated, with sets of flip-flops to remember which input is faster. It uses this to send corrective high or low pulses out to the VCO control in a phase-locked loop. In other use, it is a simple memory register, but the output pin13 needs an explanation...
The P and N transistors are not a complementary inverter, but a tri-state logic output. If both are off, it means a PLL is tracking perfectly and the VCO control voltage can be left unaltered. If the VCO is slow, then the Pmos turns on until it's back up to speed. This all comes from which flip-flop sets first and it happens on the positive edge of the inputs so doesn't care about duty cycle. So the full sawtooth scheme outlined earlier should work in a PLL despite the narrow pulse that would be fed into pin3.
By fitting pull-up and/or pull-down resistors on pin13, the flip-flops can be used for other sequential logic functions according to the order in which the input pins 3 and 14 change from low to high. If an R-C timer is controlled from pin13, you have an attack/release envelope generator or whatever you can find a similar use for.

The Phase Pulses output only goes high when both P and N transistors are off. In a PLL, that indicates it is tracking correctly. It can be used as a latching logic function according to the flip-flop states.

The internal diagram above may not be complete since I think there must some protective logic to stop both P and N transistors ever turning on at the same time, which would cause a short circuit through the chip!

[anotherjim]

I smoked this one for the Kipper 

This uses the normal VCO arrangement with the PC2 flipflops controlling the action.
R3 and C6 set the basic pitch range.

The first push of Sw1 sets pin1 high and lights the Armed LED.
The second push triggers the alarm. The Armed LED goes out.
Pin13 switches high and causes a rising pitch CV at a rate according to R2+R6 and C2. The CV is buffered by the source follower out of pin10 (aka the DEMO or Demodulate pin).
When the input pin3 sees the rising voltage as a logic high, pin13 switches low and the CV voltage falls back towards 0v via R2+R6.
When the pin9 voltage gets too low for the internal control transistor, the VCO stops and pin3 sees logical low.
It is then ready for another arm/trigger cycle.
Because of the Vgs threshold of the pin9 control mosfet, there is a delay after trigger before the VCO starts up at minimum pitch.
Additional pushes of the button during a cycle can pause it and hold pitch.

[Kipper4]

I'm touched thanks Jim.
Such circuits are very satisfying. I'll put it on the breadboard this weekend.

I've done a wailing siren with 555 chips.
I'm loving messing with the 4046.
I might do a dual 4046 or 4046/555 hybrid.
Can I ask what voltage range your using for the pitch cv.
Thanks a bunch. Hope you enjoyed the designing.

This is turning into a 4007 thread iirc......
Love it. I'm sure it will be a reference for me for a while.

[anotherjim]

Pitch CV is an output - if you want to use it to send to something else or just watch it on the scope.
Timing cap can be around 10n to 100n. pin11 resistor try 47k or a pot+10k. Sweep pot 1M and cap and C2 1uF or more.
I had a WWII Westinghouse air-raid siren type sound from mine. But I drew that from memory although I had in the breadboard recently.
It needs a volume control or it will be loud!

[Kipper4]

What value R3 please jim

Ooops got it 50k pot and 10k r series

[anotherjim]

I told you it was £"%$^%% loud!

Here's an odd one using the Xor PC1 comparator...

I drew this largely from memory so there are no valid component values there. It's one of many methods I've tried over the years to exploit the audible effects of ultrasonic sensors that I discovered when messing around with an Ultrasonic Car alarm sensor.
It's a microphone but it doesn't pick up any sound directly. It turns any movement in the path between transmitter and receiver into a voltage change. If that movement happens to be cyclic (like fan blades), then the output is audio and it does sound like a spinning fan, but it does not pick up any other nearby sound. It can be used to listen to the cone of any speaker in a multi-speaker cab, and you will only hear that speaker. Rapid movements in its path sound like martial arts combat swishes and wooshes.

The VCO is set to always run at the spot frequency for the ultrasonic sensors. The ones I find best are 40kHz commonly used in car alarms. The transmitter (Tx) can be directly driven, but for more power, it can be driven in push-pull bridge mode. These transducers are closely tuned to their target frequency and don't really care about waveform purity. The second harmonic at 80kHz won't do anything at all. Ideally, you will want to measure the transmission frequency and set it with a multiturn trimmer pot. The frequency must stay fairly constant and I think I built mine to run from a PP3 with the 4046 pin15 Zener providing supply voltage regulation for the 4046 only.
The Tx and Rx are positioned side by side to point the same way (ultrasound is very directional) and the idea is that the ultrasound waves bounce back off a subject and are picked up by the receiver (Rx).
The VCO output is sent back into pin3 comparator input and the amplified return signal from the Rx feeds pin14 signal input. The Rx signal will appear perfectly sinusoidal if you scope it.
Differences in phase between the Tx and Rx causes High pulses out of PC1 pin2 proportional to those differences. Similar to PWM audio, the pulses are averaged by an RC network and treated as audio. For the audio to be heard clearly, the Tx and Rx must not move relative to each other or the subject.

[anotherjim]

Here's a snippet with a 4046 in its intended phase-locked loop role...

The old Wasp synth uses divide by n counters to create the required key pitch from a master oscillator. This method has no means to produce a smooth portamento glide between notes like a voltage-controlled analogue VCO synth can. Each of the 2 DCO's in the Wasp feed one of these 4046 circuits before treating the square wave VCO output in waveshaper circuits.
When the input is reasonably stable and regular, this performs very well. The component values are a good starting point for new designs. It would be a good addition to an Arduino based mono-synth for example where the basic tone output is a simple square wave that cannot glide smoothly and the software complications to do that are inconvenient to do in the Arduino language.
If the Input signal is disconnected, the VCO will droop down in pitch all the way down to zero and cutoff. When the input is reconnected, it will glide up until it matches the pitch.

This is, of course, the basis of many guitar synth ideas. That those are incredibly hard to get tracking a guitar signal reliably has nothing to do with any shortcoming of the 4046. Guitar tone is not "reasonably stable and regular"!

[anotherjim]

Time to talk about chip brands.
Of all the 4000 series, it appears that for a CD4046B, who made it and when really matters. Manufacturing processes have changed since these things were first introduced and that means the quality of silicon and precision of manufacturer technically improve - mostly with the object of saving money. "We reserve the right to change or improve the product... yada yada". Even in the early days, there seem to be at least 2 main variants of the 4046 chip which perhaps ought to have carried different part numbers. They appear under several brands as second-source licensed copies.

For jellybean logic chips, brand variations have no real impact, so long as they meet the databook spec, it meets the need. For anything with a linear condition that is sensitive to transistor characteristics, it can cause unintended trouble.
There are CMOS inverter brands that get noticeably hotter than others when "misused" in linear mode due to higher current when biased as amplifiers.

In the 4046, variant differences mainly affect the linearity and min-max frequency of the VCO.
The pin 9 VCO control range lies from when the input voltage is high enough to turn it on (about 1v) and then around 1v below the positive supply there is a rapid rise in frequency as the Mosfets get close to saturation. Between these limits, it is fairly linear. If pin9 is bypassed by directly controlling the current via pin11 or pin12 resistors, control to a lower frequency minimum is possible.  Can't do anything much about the high control saturation point.

This pic shows the affect on linearity when control current as at the minimum extreme. The timing cap can no longer be charged in linear fashion. This was the same circuit that was producing a pretty decent saw wave up to and over 19kHz. I can get the low frequency working well down a whole decade by using a different brand of chip.

The best brands are...

Philips HEF4046 (now NXP)
Motorola MC14046 (now ONSemi)
National Semiconductor CD4046 (discontinued)
Hitachi HD14046 (discontinued).

The worse brands are...

Texas Instruments  CD4046 (Formally a Harris part)
ST HCF4046

Now, guess which brand 4046 are now only available in SMD packages?
The best ones of course.

In the examples I've shown, the TI part was used. I have some old Philips chips, but that would have been cheating.

I said I think there are 2 main variants. If you look in the datsheet tables, the most obvious "tell" I can see is for the Zener voltage. The best types have a Zener typical voltage of 7v. In the worst, it is 5v.

[bluebunny]

I believe Thomas Henry also had something to say about brands.  He certainly made recommendations for his X-4046 VCO and I had to hunt down a specific brand for mine.

[ElectricDruid]

I tried about four different brands when I was experimenting with using the 4046 as a high frequency master VCO for an organ/string synth note frequency divider board. Like you, I found that they varied by about 10:1. It was chaos. I could make most of them work, but I needed to change half the component values to do it. I'd already selected the parts to some extent, since different brands state different maximum operating frequencies, and I was looking for something that could run up around 8MHz, with scope to go higher/lower to allow frequency modulation (vibrato for starters, but hopefully more than just a little wobble).

Given that I had hoped to make the thing into a nice friendly DIY project ("just plug these parts in and it works!") it wasn't really happening. That project has never made it off the back burner, or at least not yet. That's partly why I[m watching developments here with interest. You might turn something up that can save that project.