changing bias on MU amp has no audible effect

[Boner]

I've built me up a mu and and although it sounds really nice, changing the bias has NO audible effect.

http://www.geofex.com/Article_Folders/modmuamp/modmuamp.htm

In mine I'm using a PF5102 for the bottom JFET and a J105 for the top (I have em, and they seem to work well enough). In the geofx article you can't change the bias, but I replaced the 2 10k ohm resisters with a 50k pot and checking voltages, there is a change from 2.5 to 7 volts DC point on the output. Although I am tapping the output at the bottom JFET drain as opposed to the top JFETs source.

Any ideas? I'm using a 4.7M and 100nF cap just like in the article.

*edit*

forgot to mention that mocking the circuit up in multisim, changing the bias the way I am has a very noticeable effect on clipping symmetry.... so it SHOULD be working right? loolol

[Kipper4]

I'm no expert but I dare guess you are changing the DC  bias and expecting an AC gain change.

[Boner]

I'm no expert but I dare guess you are changing the DC  bias and expecting an AC gain change.

was hoping to change the symmetry of the clipping.

[Kipper4]

And what does the oscope say?

[anotherjim]

Maybe the lower FET can't bias properly anyway with gate and source referenced to 0v. Try inserting resistance in the source-0v to raise source volts and add more -Vgs. If it works but reduces gain too much, you can always bypass the resistor with a cap.

[amptramp]

If you are going from the geofex article linked in the first post, there are three diagrams and the final one is the shunt regulated push-pull stage (SRPP).  The first two diagrams use the upper transistor as a current source of high impedance, so the gain of the stage is very high, but it is in parallel with the load impedance, so it comes down a little.  In the second drawing, the load impedance is the third transistor gate, so the impedance and the gain are very high.

The third drawing operates on a totally different principle.  The upper transistor is a gain stage but it is inverted with respect to the lower transistor so when the circuit input goes positive, the lower transistor conducts more current, meaning the resistor between the lower drain and the upper source takes more current and drives the upper gate lower with respect to the upper source.  When the circuit input goes negative, the lower transistor conducts less current and the bias on the upper transistor is reduced, meaning it draws more current.

If the resistor between the lower drain and upper source is equal to the reciprocal of the upper transistor transconductance, the swing of the upper transistor is equal to the swing of the lower transistor and the amplification is symmetrical between upper and lower transistors.  But here's the catch: the upper transistor current is in series with the lower transistor so the difference in current has to be taken by the load.  If the load impedance is too high, the output will slam against the rails, so one way of getting a variable fuzz out of an SRPP stage is to vary the load impedance and with the correct resistance between lower drain and upper source as mentioned above, it is symmetrical.  If you make this resistance variable, you can make the fuzz asymmetrical.

[Eb7+9]

When running simulations using jFET transistors it's s good idea to adjust device model Vgs(off) to their measured values beforehand ... otherwise pretty meaningless

[iainpunk]

i understand why and how the mu amp should work, but wont a SRPP be an easier and better way? or even the j-fet and diodes version, see pic related, you can change the bias with different types of diodes.

[Boner]

Unfortunately I don't have an oscilloscope right now. 

Forgot to mention I have a 1k resister and a 220u cap on the lower jfets source. With the top being a J105, no bias change. if I replace it with a pf5102 (so now both are pf5102) I can adjust the bias symmetry 

I'm guessing if the tops Idss or Vgs is too big it won't work? 

The third drawing operates on a totally different principle.  The upper transistor is a gain stage but it is inverted with respect to the lower transistor....

The upper jfet is inverted? As in its p-channel instead of n-channel OR is the actual jfet inverted so source/drain are flipped?

[amptramp]

Unfortunately I don't have an oscilloscope right now. 

Forgot to mention I have a 1k resister and a 220u cap on the lower jfets source. With the top being a J105, no bias change. if I replace it with a pf5102 (so now both are pf5102) I can adjust the bias symmetry 

I'm guessing if the tops Idss or Vgs is too big it won't work? 

The third drawing operates on a totally different principle.  The upper transistor is a gain stage but it is inverted with respect to the lower transistor....

The upper jfet is inverted? As in its p-channel instead of n-channel OR is the actual jfet inverted so source/drain are flipped?

As explained, when the current increases through the lower transistor, it reduces through the upper transistor and vice versa.  It is as if the transistors were connected to inputs that moved in the opposite direction, but the upper transistor bias is derived from the current and thus, its effect is as if it was driven by a separate source of opposite polarity.