Complementary feedback stage biasing

[Fancy Lime]

Hi there and happy New Year!

I'm trying to build a stage with this topology:
https://2.bp.blogspot.com/_zvebWsI5UUg/TDZxFEu1d4I/AAAAAAAAANY/bfizAIyAiJ8/s1600/JFETBJTFBAMP.png
which I found here:
https://apocalypseaudio.blogspot.com/2010/07/circuit-splinter-no2-sziklai-pair.html
There are numerous iterations of this out there, it has been discussed here before as well. However, I am unable to find usable design guidelines for this thing. Or what it is actually called, for that matter. "complementary feedback stage" probably isn't the proper name. Most importantly, I'd like to know how to bias this thing (so where do I want what voltage). Yes, I could try to bias by ear but I'd rather know what I'm doing before I start randomly fiddling with resistor values. Are there any commercial circuits in the guitar realm that use this? DIY designs? Pros and cons of this design approach? Looks like it may make a decent input boost stage for a preamp or distortion or a booster slightly of the beaten path. The feedback voltage divider R5/R3 virtually begs for the addition of some caps and resistors to do a bit of interesting tone shaping. Or clipping diodes.

Cheers,
Andy

[rankot]

Similar to Xotic EP Booster, except that EPB doesn't have this feedback resistor, has some filtering added and use NPN as the output.

http://revolutiondeux.blogspot.com/2012/01/xotic-ep-booster.html

[Fancy Lime]

Similar to Xotic EP Booster, except that EPB doesn't have this feedback resistor, has some filtering added and use NPN as the output.

...

So... not really similar then, is it? The EP has a common emitter NPN stage for Q2 and the other circuit has a common collector PNP there. And the negative feedback does something or other to the bias of Q1. Plus the stages are DC coupled, unlike in the EP. Totally different topology if I'm any judge. Although google kept pushing the EP on me when I tried to find info on the Apocalypse Audio circuit.

Andy

[Steben]

These two transistor stages are very interesting pieces for designing guitar circuits.
But some things are not to be ignored. The classic Fuzz Face circuit is basically one of the classic two transistor stages invented long before to maximise gain.
The one you think of is another. Yet do not forget the fuzz face circuit has its dynamic musical character unrivaled by others.
This circuit actually has high input impedance even with BJT instead of FETs. The feedback helps expanding linear functioning. Both completely the opposite of the FF circuit.

Another interesting two transistor circuit is the axis fuzz:

[rankot]

Some info here: https://en.wikipedia.org/wiki/Complementary_feedback_pair

[R.G.]

You've given yourself a tough task. Biasing a CFP with bipolars isn't too tough, but biasing with a JFET is intrinsically harder, because of the variation of the Vgs needed to hit a specific bias point.

I ran into this in setting up the input stage for my boards recreating the Thomas Organ Beatle V1143 amps. They use a variation of this circuit.

It's easiest to understand it by working back from the output. You want the output to be roughly in the center of the power supply in most cases, so the collector voltage of the PNP is going to be half the power supply, more or less. That means that resistors R5 and R3 in series will have to have about half the power supply across them. Then the source voltage of the input JFET will be half the power supply times R3/(R3+R5).

Now the rub. R5 and R3 are set in a 9:1 ratio by the need to set the closed loop gain to 10. So the source voltage at the JFET is fixed. The gate is held at ground, so the gate voltage is fixed. That means the JFET has exactly one Vgs at which it is set for these circuit conditions. While it is possible that any given JFET >might< be able to bias at that set of conditions if the source voltage is within the range of the Vgsoff of the JFET, but actually making that come true will mean picking through JFETs for the right one, or modifying the resistances to get the voltages and currents come out.

The JFET is the input "differential amplifier" of this feedback amplifier. The source is its inverting input. The DC idle current through the JFET raises the voltage through R3 in combination with the current fed back through R5. So the ratios of the currents through R3 and R5 reflect the necessary currents to make the JFET and PNP run correctly.

With the ratios of R5 and R3 fixed by the necessary gains (*note that these can be tinkered by using caps to change the AC and DC feedbacks*) you have the levers of the values of R2 and R4 to pull. The Vbe of the PNP is relatively fixed. It's going to be 0.5 to 0.7V. The value of R4 sets the transconductance of the PNP - how much current flows in the PNP for a certain change in its base voltage. The value of R2 sets the voltage on the base of the PNP for a change in current in the JFET. Both of these are involved in the open loop gain and the idle bias of the pair. And even better, they are relatively free of the "outside" needs of the amplifier, where R3 and R5 are mostly fixed; certainly their ratios are.

R4 is a good place to change the overall open loop gain of the amplifier. If it's small, the transconductance, and voltage gain of the PNP is very large. If it's big, the transconductance is small. R2 controls the percent of the JFET drain current that is shunted into the PNP. If it's small, the JFET can pump a lot of current through it and not affect the PNP so much. If it's big, nearly all of the JFET drain current flows through the base of the PNP.

So taking all this together, pick your output voltage. Set the closed loop gain with the feedback network with R5 and R3 and any other tinkering you need to the feedback conditions. Pick the operating idle current through the PNP by setting the value of R5 and R3.

Pick a JFET that has the possibility to run with the Vgs voltage that R3 has to have across it. This effectively means that the JFET selection is part of the biasing strategy. It's good if the JFET works at quite low currents, as you want the JFET current to not upset your ideal feedback current through the PNP and R5, so small is good. High gain is not needed much, as the PNP in this setup is quite capable of producing high gains. With a nominal Vgs of the voltage across R3, find what DC current is likely to result from a typical JFET of the type you pick.

With the DC current in the output set by the total current you want and the values of R3 and R5, you can set the sensitivity of the PNP by varying R4. For most setups you want R4 quite small compared to R5, so it doesn't upset the output DC conditions much. It varies the open loop gain (and hence linearity, distortion and stability) of the overall amplifier a lot. R2 varies the proportion of the JFET current that gets into versus bypasses the PNP base, so it's the major determinant of idle current in the PNP, and hence the total current in R3/R5 and the overall idle of the circuit.

It's R2 and R4!

[jubal81]

Definitely going to need to be biased. Instead of connecting R1 to ground, connect it to a voltage divider with a bypass cap at that node - like you're biasing an opamp.

I use a scope to bias - adjust the voltage until the rail clipping is even on top and bottom. This will vary depending on the JFET you use. Another thing to consider is adjusting R2 and R3 to limit current on JFET to about 70% of its IDSS.

Another cool thing about this setup is that it's non-inverting.

[Steben]

You've given yourself a tough task. Biasing a CFP with bipolars isn't too tough, but biasing with a JFET is intrinsically harder, because of the variation of the Vgs needed to hit a specific bias point.

I ran into this in setting up the input stage for my boards recreating the Thomas Organ Beatle V1143 amps. They use a variation of this circuit.

It's easiest to understand it by working back from the output. You want the output to be roughly in the center of the power supply in most cases, so the collector voltage of the PNP is going to be half the power supply, more or less. That means that resistors R5 and R3 in series will have to have about half the power supply across them. Then the source voltage of the input JFET will be half the power supply times R3/(R3+R5).

Now the rub. R5 and R3 are set in a 9:1 ratio by the need to set the closed loop gain to 10. So the source voltage at the JFET is fixed. The gate is held at ground, so the gate voltage is fixed. That means the JFET has exactly one Vgs at which it is set for these circuit conditions. While it is possible that any given JFET >might< be able to bias at that set of conditions if the source voltage is within the range of the Vgsoff of the JFET, but actually making that come true will mean picking through JFETs for the right one, or modifying the resistances to get the voltages and currents come out.

The JFET is the input "differential amplifier" of this feedback amplifier. The source is its inverting input. The DC idle current through the JFET raises the voltage through R3 in combination with the current fed back through R5. So the ratios of the currents through R3 and R5 reflect the necessary currents to make the JFET and PNP run correctly.

With the ratios of R5 and R3 fixed by the necessary gains (*note that these can be tinkered by using caps to change the AC and DC feedbacks*) you have the levers of the values of R2 and R4 to pull. The Vbe of the PNP is relatively fixed. It's going to be 0.5 to 0.7V. The value of R4 sets the transconductance of the PNP - how much current flows in the PNP for a certain change in its base voltage. The value of R2 sets the voltage on the base of the PNP for a change in current in the JFET. Both of these are involved in the open loop gain and the idle bias of the pair. And even better, they are relatively free of the "outside" needs of the amplifier, where R3 and R5 are mostly fixed; certainly their ratios are.

R4 is a good place to change the overall open loop gain of the amplifier. If it's small, the transconductance, and voltage gain of the PNP is very large. If it's big, the transconductance is small. R2 controls the percent of the JFET drain current that is shunted into the PNP. If it's small, the JFET can pump a lot of current through it and not affect the PNP so much. If it's big, nearly all of the JFET drain current flows through the base of the PNP.

So taking all this together, pick your output voltage. Set the closed loop gain with the feedback network with R5 and R3 and any other tinkering you need to the feedback conditions. Pick the operating idle current through the PNP by setting the value of R5 and R3.

Pick a JFET that has the possibility to run with the Vgs voltage that R3 has to have across it. This effectively means that the JFET selection is part of the biasing strategy. It's good if the JFET works at quite low currents, as you want the JFET current to not upset your ideal feedback current through the PNP and R5, so small is good. High gain is not needed much, as the PNP in this setup is quite capable of producing high gains. With a nominal Vgs of the voltage across R3, find what DC current is likely to result from a typical JFET of the type you pick.

With the DC current in the output set by the total current you want and the values of R3 and R5, you can set the sensitivity of the PNP by varying R4. For most setups you want R4 quite small compared to R5, so it doesn't upset the output DC conditions much. It varies the open loop gain (and hence linearity, distortion and stability) of the overall amplifier a lot. R2 varies the proportion of the JFET current that gets into versus bypasses the PNP base, so it's the major determinant of idle current in the PNP, and hence the total current in R3/R5 and the overall idle of the circuit.

It's R2 and R4!

200% hitting nails.
Question is as I tried to say: why use a Jfet? One of the advantages of two BJT transistors anyway is having so much possibilities in getting gain and high input impedance. With almost as much parts you can even DC couple an emitterfollower buffer and a common emitter stage. We don't need mega and mega ohms for a guitar.
The non-linear behaviour of the FET is going to be nearly completely cancelled out by biasing and feedback. The best qualities soundwise of jFETs are in single stages or mu-amps (which are close to single stage).
Check this:
https://www.electronics-notes.com/articles/analogue_circuits/transistor/amplifier-npn-pnp-two-transistor-circuit.php

[R.G.]

My guess is that the concept behind using a JFET was to get a naturally high input impedance with the input held at ground by a single biasing resistor. It allows you to eliminate a capacitor at the input if you want, and not have to mess with the added parts involved in bootstrapping the input.

[Rob Strand]

You can separate the AC gain and DC biasing by using a partially bypassed source/emitter on the first stage.

Some examples here,
https://www.eeeguide.com/two-stage-direct-coupled-bjt-amplifier-circuit/

You don't really need the bypassed emitter resistor on the second stage.

The Boss discrete opamps circuits, like that used in the BD-2,  are basically the same idea except the first stage is a diff-amp instead of a single ended stage.

[Fancy Lime]

Hey guys,

thanks for the infos!

@R.G.
your explanation is pretty much exactly, what I was looking for, thanks!

@Rob
nice resource, thanks! True, that "discreet opamp" in the BD-2 looks quite similar. Basically just an additional JFET buffer in the feedback path, if you want to look at it that way. I wonder if Boss really bothered with selecting JFETs by V_{GS (off)} or if the design they used is tolerant enough to just use any old 2SK184 with the JFET bias at half supply voltage. Interestingly, the 2SK184 they used seems to be identical with the 2SK117, of which I have a bunch, apart from the package. Maybe I should start with the boss design as a reference then... hmm, food for thought.

The one remaining question is how the JFET-BJT version compares to the BJT-BJT version, performance wise. I vaguely remember to have read somewhere a long time ago what Steben also stated, namely that the BJT-BJT version has a pretty high input impedance as well. The question is, how high. Normally with common collector cisrcuits, we are happy to get in the tens of kiloohms, so what does "high" mean here. That is the main question for deciding when wrestling with the somewhat more troublesome biasing of a JFET is worth the trouble and when we can just as well content ourselves with a BJT input.

Cheers,
Andy

[R.G.]

You might want to look at the onboard preamp article at geofex: http://www.geofex.com/FX_images/Onboard_Preamp.pdf

Although this was designed up for a gain of unity and not quite exactly the same, it has an input impedance of several megohms from tests in simulation. It also does not bother with bootstrapping the input. A bootstrap path to the input can kick input impedance up to quite high.

Note that the focus of the onboard preamp was low total current draw consistent with being powered by two coin cells for a long time. That drove other facets of the design.

[Rob Strand]

I wonder if Boss really bothered with selecting JFETs by VGS (off) or if the design they used is tolerant enough

The Boss JFETs have fairly low Vgs_off, so wherever the JFET gate voltage needs to sit (which is constrained within 0 to Vgs_off) it's going to be a small variation compared to the 9V rails.   If you have JFETs with a Vgs_off of 4V then you would expect the circuit voltages and performance to depend on where exactly Vgs_off ended up. 

In your original circuit, the single ended circuit isn't as friendly as the diff amp,
https://2.bp.blogspot.com/_zvebWsI5UUg/TDZxFEu1d4I/AAAAAAAAANY/bfizAIyAiJ8/s1600/JFETBJTFBAMP.png 
The top 470R resistor R2 has about 0.65V across it, so when if no current flowed through the R5 (4k7)  the voltage across R3 would also need to be 0.65V.  That's only 0.65V across the gate source.  The DC bias voltage would be at 0.65V since no current flows through R5.

To get 4.5V at the output some current would need to flow through R5.  The extra current down R5 would raise the source voltage by roughly 0.38V ( = (4.5-0.65)*R3/R5) so the source will sit at roughly 0.38+0.65 = 1.03V.   The drain current comes from 0.65/R2 = 1.4mA. So for the circuit to be biased with 4.5V at the output the JFET characteristic *must* pass through Vgs=1.03V and 1.4mA.  It's unlikely you will get that  so the DC voltage at the output will be off.    Also, the Vgs_off for the JFET would need to be some safety margin greater than 1V in order for it to operate at Vgs=1V.   You can tweak R2 to adjust the DC bias point for different JFETs.   Decreasing R2 will increase the drain current and increase  the Vgs operating point and that weak should work very well in coping with different JFETs.

I vaguely remember to have read somewhere a long time ago what Steben also stated, namely that the BJT-BJT version has a pretty high input impedance as well.

Feedback pushes up the input impedance *provided* the stage isn't clipping.  In clipping the JFET stays high impedance and the BJT will be lower impedance.

[Steben]

I vaguely remember to have read somewhere a long time ago what Steben also stated, namely that the BJT-BJT version has a pretty high input impedance as well.

Feedback pushes up the input impedance *provided* the stage isn't clipping.  In clipping the JFET stays high impedance and the BJT will be lower impedance.

Classic one stage BJT Impedance - as in a common collector - is in a thumb rule parallel impedance of the biasing resistors and the impedance of the transistor.
R1 // R2 // Rbase with Rbase = hfe * (Re).
Re is usually around 4k7 to 10k in common collectors with hfe around 200 to 500. This leads to Rbase of a small one Mohm to 5 Mohms......
With all biasing resistors at 1 Mohm and Rbase at 1 Mohm, you have a "low" input impedance of 330k. You see what I am getting to?
Yet as I said, thumb rule with no feedback or bootstrapping involved. Bootstrapping pushes this all way up.

IMHO Clipping of an input stage is not a good idea, if that input stage isnt designed to sound good at clipping. If so, a single jFET stage is superior.


On the other hand i did find this:

[R.G.]

The 2N3819 has a Vgsoff spec of -8V max. That is, you >might< have to apply as much as a bit less than 8V to get the thing to turn off. There are no entries at all for the minimum and typical Vgsoff in the datasheets I looked up just now (On Semi and Central Semiconductor). That thing is going to have to get several volts across R2 to get the current in the JFET low enough to keep the base current in the PNP low enough to bias this thing within the 12V power supply.

That is - it's not likely that this circuit will bias near half the power supply with nominal JFETs. It will almost certainly bias SOMEWHERE inside the power supply, which makes it best suited for low level, low signal amplification. That makes sense, as the 10k/82 ohm feedback network shows that it's closed loop gain is high.

[rankot]

This datasheet says that typical V_gs(off) is -3V.
http://www2.eng.cam.ac.uk/~dmh/ptialcd/jfet/2N3819.pdf

[Fancy Lime]

Typ ≠ max

[rankot]

I know, but RG said there's no info on typical value in his datasheet, so I found this. Max is the same in both: -8.0V.

[PRR]

....i did find this:

Some of those "example circuits" are real dubious.

It happened I had the "same" plan open in Pspice, with a '3819 (I was plotting temperature sensitivity, another can of worms). I edited the values to match the "found" plan. With a nominal '3819 of Vto exactly 3.0 the output biased to 10.2v of a 12V supply, "nearly jammed". "Works", but not usually where we want to be. There's only 1:2 ratio of current from 1st stage to 2nd stage, where we'd usually like more current in each successive stage.


> closed loop gain is high.

Well, someone "hopes" it is high. Jammed-up like my sim, gain was low. Some tinkering did give Vc near half supply and gain like 40dB. But it took a 3-way tinker to get the DC balanced. And parameters of real parts are wide.

Aside from messy DC function, note that the current gain inside the NFB loop is only hFE. Working from Gm of FET, the open loop voltage gain can't be huge.