Matching capacitors in phasers?

[ljudsystem]

I've been reading R G Keens great article on the technology of phase shifters and flangers (http://www.geofex.com/Article_Folders/phasers/phase.html) and it got me thinking.

It's common to use matched sets of fets or opto-couplers for phasers, I bought a mathed quartet  of jfets for my Phase 90 build for instance. I know it's harder to do, but wouldn't it also make sense to match the capacitors? 

Would it make any difference sound wise?

[Rob Strand]

Matching the caps isn't solving the same problem as matching the JFETs.

When you match JFETs you are matching Vgs_off.  The reason it is important is small differences in Vgs_off cause large differences in the JFET resistance when the control voltage (ie. the LFO output) is near Vgs_off.

If you look-up JFET resistance you will see it take the form,

Rds =  rds0 / (1 - |Vgs / Vp| )

where Vgs is the gate source voltage, Vp  is the Vgs_off parameter for the JFET, rds0 is the minimum resistance of the JFET.

Take the case of 50mV matching,
if Vgs = 0.9 and Vp = 0.95 you get Rds = 19 x rds0
and if Vgs = 0.9 and Vp = 1.0 you get Rds = 10 x rds0

So even though the Vp values 0.95 and 1.0 are quite close in percentage terms the resistance almost doubles.
In other words when Vgs is near Vp the resistance becomes very sensitive to a mismatch in Vp.

If you had caps 47n and 0.95*47n the effect is only 1 vs 0.95  which isn't very sensitive to the change in the cap value at all.

[Typos fixed]

[ljudsystem]

Ok, thanks. Math isn't my strong suit but I get the general idea.

[Mark Hammer]

Matching of caps in phasers is moot because the effect is a result of the cumulative phase shift across all the stages, not the distribution of phase shift in any one stage.

Matching of LDRs is also unnecessary, because it is very rare that an LDR will not show resistance-change in response to degrees of illumination.

In contrast, one strives to use FETs that are very close in characteristics, such that a bias setting can be identified which allows all FETs to change their drain-source resistance at the same time, and not have any that stop changing at one or the other "turnarounds" (peak and trough of sweep).

[PRR]

> matched ...jfets for my Phase 90 ...make sense to match the capacitors?

A capacitor is made to be within 10% of its marked value. The highest is 1.2X the lowest.

JFETs can't be made that exactly. "Same part number" may vary by 7:1 or more. In both current and voltage (thus resistance).

[ljudsystem]

Ok, interesting. I'm breadboarding a four stage led/ldr phaser/vibe for the moment. I've got one led for each ldr with a trimpot parallell to the led trying to match the high an low ends of the swing. But maby this is pointless? Should I just go uni-vibe style and use a single led for all four stages?

[Rob Strand]

JFETs can't be made that exactly. "Same part number" may vary by 7:1 or more. In both current and voltage (thus resistance).

Idss and Vp are correlated.  So despite Idss and Vp having crappy tolerances the channel resistance (rds0) is relatively tight.

IIRC,
           Idss varies a cube of a channel design parameter,  and has the worst variation.
           VP varies as the square
           rds0  = Vp /  (2* Idss)  only varies linearly  (as the cube and square dependencies cancel out)
           so rds0 has the tightest specs and it occurs by nature.

           You will see a lot of JFET bundled around 200 to 300 ohms regardless of the Part number, VP, Idss

The key point is the subtraction in 1- |Vgs/VP| emphasizes  the tolerance in the *voltage controlled* resistance; and only when Vgs is near Vp.

[Eb7+9]

Would it make any difference sound wise?

Of course, otherwise all phasers would sound exactly the same ... case in point, consider Univibe and Resly Tone cap values

The all-pass stages that create phasing react to the RC product between jFET channel resistance and associated cap ... so if you wanted matched stages against varying R values you would compensate by inversely proportioning the associated C value to each individual Rmin value

where Rmin = Vgs(off)/Idss

say, in an extreme case example, we didn't have access to matched devices but just so happen to have a bunch of different type devices with exactly same Vgs(off) value; and of course with wildly differing Idss values and, hence, Rmin values ... even in this case we could still build a balanced phaser if we aimed to do so

having matched all-pass stages is an engineering thing, one which will give you the deepest and narrowest notch(es) ... however, in musical settings breaking those rules might lead to other "interesting" types of response

like sticking Univibe cap values in a Small Stone phaser, done years ago

as Rob pointed out jFETs show an Vgs(off)&Idss trend that isn't perfectly constant ... you can use the simple 9v-battery-DMM tests to extract the Vgs(off) and Idss values of your devices to see how well matched they are, both in terms of control range and Rmin values

as well, you can experiment with differing cap values assuming you can measure them ... see for yourself what it sounds like when you make your RC products bang-on identical (or close) and when you randomly offset them by 10~20%

as we know you're not likely to end up with something that ever sounds bad, the question is will you get something that sounds markedly better when all are the same time-constant wise ... assuming they are all sweeping in unison properly (a matter of Vgs(off) matching)

to answer this last question please post the Vgs(off) and Idss values for your four special select devices ...

[ljudsystem]

No, I'm using LEDs not Jfets. LEDs don't have Vgs and Idss values... right?

[Mark Hammer]

The question is "What are you aiming for, tonally?".  If you are simply aiming for a phasing effect, then nominally-similar cap values will be good enough.  FET matching is a question of whether the circuit will exhibit acceptable sweep characteristics, without any one or more stages "choking".  If one is using LDRs, there is very little reason to anticipate such "choking", so attention shifts to whether the LDR and cap properties will produce some specific sound.  But as I say, if all you want is a phasing effect that sounds musical to your ears, "ballpark" similarity of components will be quite acceptable.  Perhaps more critical would be the dynamic characteristics of the LDRs you are using.  If they have particularly slow recovery times, then there may be limitations on sweep width when using faster LFO speeds.  Conversely, if they exhibit very fast response times, that may yield jarring jerky sweeps.

[ljudsystem]

Interesting, is that related to the difference between light and dark resistance?

[Eb7+9]

No, I'm using LEDs not Jfets. LEDs don't have Vgs and Idss values... right?

correct ... either way you have incentive to eliminate mismatches ... it may mean matching photocells or opto-couplers ... in the later case matching the drive mechanism as well ... the same idea wrt cap balancing applies here as well

[Kipper4]

Which Phaser design did you go with in the end.
I'm investigating some phaser based projects and experimenting with some ideas for future project and sharing what I'm learning.

You have the best guys help here from the above.

[PRR]

> despite Idss and Vp having crappy tolerances the channel resistance (rds0) is relatively tight.

Of course. But we also want an even swing to Rds(max). Control voltage is related to Vp, so Vp must be close (or trimmed) on all devices in the array.

[Kipper4]

PPR you got me there.

"(or trimmed)"
Do you mean individual trimmers for each fet?

The nearest thing I can think of that does something similar with its 2x 10k trimmers in the bassballs.

Link to a drawing
http://guitarpedalbuilders.blogspot.com/2013/01/ehx-bassballs-schematic.html

In effect two tractors chained back to back travelling in opposing directions is better than the same two tractors going in the same direction.

[Mark Hammer]

Interesting, is that related to the difference between light and dark resistance?

What you want in a phaser is that all the control elements, whether JFET, OTA, LDR, or PWM switched-resistance, all continue to change throughout the sweep cycle.  While there IS a minimum and maximum resistance of any LDR, in reality, they seem to very rarely be reached. The result is that the cumulative phase shift, summed across all stages, keeps changing and moving the location of the notches produced.  For the most part, OTAs, as used in the Small Stone and many other phasers, also don't have any sort of practical max or min in their sweep.  However, they have headroom limitations, which LDRs do not have.

[Rob Strand]

"(or trimmed)"
Do you mean individual trimmers for each fet?

You can definitely do that and it does work but in practice it's a pain to adjust correctly.

When you match JFETs you do it on the bench by measuring each JFET in isolation.  The measurement is very easy,  a nice stable a DC voltage.   Once matched you only have one bias adjustment on the pedal and that is relatively easy to adjust.  It's enough take up the small difference in the JFETs.   Most people do this by ear.

If you try to tune 4 (or more) separate trimmers by ear it takes a long time and if you aren't savy on what to listen for it could end-up being worse than a single trimmer!

Unless you buy a large number of JFETs to sort or buy matched sets it's inevitable you will have to make a compromise in how closely you can match the JFETs.   A compromise is to bundle the JFETs into two groups, sorted by VP.  In theory you can have two trimmers one for each group.  However, since you have already measured the FETs you have a good idea of the VP differences between the two groups.  So what you can do is set-up the bias network so it produces two bias voltages but only use one trimmer.  One bias voltage being slightly different to the other and just enough to push the bias voltage towards the VP's in the second group.   This is a good way a DIY pedal can get  good performance with limited JFETs.

[Eb7+9]

"(or trimmed)"
Do you mean individual trimmers for each fet?

You can definitely do that and it does work but in practice it's a pain to adjust correctly

not if you know what you're doing ...

I outlined a method and provided a perfectly working circuit to show how to do it ... pay attention to the LFO section, in particular the offset control and how that works

https://viva-analog.com/the-paradigm-shifter/

The question becomes, can we (or not) adapt the classic shifters to adopt a similar technique; and if not then why ?!

[Rob Strand]

I outlined a method and provided a perfectly working circuit to show how to do it ... pay attention to the LFO section, in particular the offset control and how that works

https://viva-analog.com/the-paradigm-shifter/

The question becomes, can we (or not) adapt the classic shifters to adopt a similar technique; and if not then why ?!

I've got no doubts it *can* be made to work and your configuration is the way to do it.   More or less an 'n pot' method of what I mentioned in the last paragraph.  Obviously more effort to set-up but one of the few ways of successfully handling JFETs. with large VP differences.

One *small* criticism is that the VP measurements are done on a multimeter voltage range and the pots are set with the multimeter resistance range.   Some meters aren't so accurate (on any range and despite the *resolution*) so the accumulation of the errors means it isn't actually as good as you would expect.   I'd set the master pot to min, so the pots are driven by the low impedance.  After that one way is to measure the divider voltages directly using the same meter scale as the measurements VP (the target voltages allowing for meter impedance loading).    [There's an even better way which factors out the meter accuracy and meter loading but it's too geeky to explain - you would probably get it though.]

Nice graph of Idss and VP you can see how both are correlated and the "unknown" ones are clearly different.

[Eb7+9]

I've got no doubts it *can* be made to work and your configuration is the way to do it.

Only a very basic level of competence is required here Rob ... I certainly appreciate you taking a look btw

Obviously more effort to set-up but one of the few ways of successfully handling JFETs with large VP differences.

I must ask, what's more effort ?! Measuring the specs of four devices and setting three trim pots or measuring a hundred or two devices and then singling out a quad that still won't be bang-on anyway ??!??!

One *small* criticism is that the VP measurements are done on a multimeter voltage range and the pots are set with the multimeter resistance range.   Some meters aren't so accurate (on any range and despite the *resolution*) so the accumulation of the errors means it isn't actually as good as you would expect.   I'd set the master pot to min, so the pots are driven by the low impedance.  After that one way is to measure the divider voltages directly using the same meter scale as the measurements VP (the target voltages allowing for meter impedance loading).

... ok let's talk baby error analysis

the master drive pot is 5k, going into a 1meg pot might "at worse" incur a 0.05.% loading error, like the hair on a flea's back ... then going into the gate of a jFET at say 1e15 ohms gives less than the hair on a newborn flea's back (ie., not even worth calculating) ... so your master pot setting argument is really meaningless here I'm afraid

as for meter error I suspect you're still working with the analogue variety ...

the meter I'm using (a Circuit Test DMR 6000) exhibits +/-0.5% error on DC Voltage readings and +/-0.8% error on Resistance readings ... since the errors get compounded in this case this gives a +/-1.3% error total

not sure if that's what you meant by *small* criticism ?!

You gotta understand all these arguments figure in my mind before I decide on a final circuit design approach (pretty typical thing in bone-fide analogue circuit design no?!) ... why would I post a circuit solution that overlooks such things ?!

I'm glad you brought this up though - it's worth going over ...

[There's an even better way which factors out the meter accuracy and meter loading but it's too geeky to explain - you would probably get it though.]

LOL ... I'm sure I would get more than you think ...
false presumptions can cause the mind to distort



please geek away if you think you can actually provide something tangible ... careful assuming you can beat the accumulated error my solution exhibits as I have a pretty good sense of possible competing approaches ... still I'm open minded, let's see what you got!

Nice graph of Idss and VP you can see how both are correlated and the "unknown" ones are clearly different.

Yup ... so-called fake Chinese devices
nothing fake as far as "perfectly usable" is concerned ...

===

So, in conclusion ... this approach, when done properly, should produce better matched all-pass performance once phasor caps are well matched as well ... and since we are only interested in relative capacitor values (as opposed to absolute value accuracy) seems we could bring the interstage component errors to well within 2% quite easily

If, on the other hand, Vgs(off) were to be measured using something like an Atlas tester, where Vgs(off) is extracted at the 5uA line, then the error levels rise dramatically; to probably something like 5~10% ... it's hard to say exactly in advance because we'd have to extract numbers both ways and do a bit of math to determine the exact accumulated error difference