Super Buffer: can't figure it out...

[niektb]

Okay, I'll admit it. I'm hopeless and I'm stuck. Following https://www.diystompboxes.com/smfforum/index.php?topic=125005.0 I thought it to be fun to design some sort of Super Buffer schematic and inject that in some pedal designs to see what happens...

However, (as happens in all engineering) I've encountered some hiccups along the way. Now I finally have a working schematic (even though I hope to make some additional changes such as bootstrapping the JFET and replacing the JFET source resistor with a Constant Current Source) but, if the simulation is any good, the Harmonic Distortion is still a whopping 1.7% (1kHz, 1V input) which is not quite what I had hoped.

Here I have a schematic with voltages at some 'strategic' points that hopefully give you some grasp


Basically what I'm trying is a high-Z JFET input followed by a BJT (to reduce output impedance that would be pretty high otherwise).
In essence I'm trying to reproduce and adapt Figure 12 from this article: https://sound-au.com/articles/followers.html#s6
To improve linearity I replaced the BJT emitter resistor with a Constant Current Source. I also put a DC-blocking cap inbetween (cause the output of the JFET seemed to be a poor bias for the BJT)

I'm not very experienced when it comes to analog designs so I hope somebody can give me some pointers or something to read that might help me figure this out. Thanks in advance!

[antonis]

Get rid of the Fet and bootstrap T2 bias via another BJT..
(ingnore dual supply and particular items values - posted just for a configuration example..)



P.S.
It should be a good idea to bias T2 (Q1 above) Emitter a bit higher than Vcc/2, 'cause you don't deal with an ideal current source hence T2(Q1) curremt sourcing/sinking abilities aren't equal..

edit: Didn't notice 10k/15k bias, so ignore the above P.S. but lower 470k resistor down to ten times (47k -56k) 'cause it will bootstrapped..

[niektb]

I had a little breakthrough by re-biasing the JFET and eliminating the BJT bias! Tweaked a couple resistor values also. Distortion is now 0.13%, much better but not quite there yet...


Edit: forgot DC voltages

[Rob Strand]

FWIW, one of the down-sides to the JFET with a source-resistor is the small gain drop.   Putting a current source on the JFET helps fix that problem.  That's the main improvement in Boss's Waza buffer.

You could adapt that idea to your circuit with a second current source.

The Waza and best buffer problem come-up a while back,   
https://www.diystompboxes.com/smfforum/index.php?topic=122929.0
Waza buffer,
https://postlmg.cc/CzVHqrh3

The Sziklai pair (100% feedback) seemed to have a slight advantages over the other forms.

The current source at the output like you have can help drive capacitive loads a little better.  There was another thread about that, (reply #22 shows waveforms),

https://www.diystompboxes.com/smfforum/index.php?topic=121891.0

Sometimes this stuff comes down to splitting hairs and/or solving different aspects of the problem.

[PRR]

> this stuff comes down to splitting hairs and/or solving different aspects

Or just using a TL072.

[antonis]

If you insist on using discrete devices buffer & JFET input, utilize at least a push-pull configuration for reducing the effect of loading in linearity..
(THD of T2/T3 stage should be halved.. - but, as already told, you also have to do something for JFET input stage.. )

[PRR]

> at least a push-pull

Your added 10uFd can't do much because T4 clamps that node.

[antonis]

No intention to argue, Paul..
(although it is proven to work quite well on constant-current source consisting of two series diodes..)

P.S.
Ignore the above..
Just realized T4 V_CE "absorbs" T2 Collector voltage fluctuation..

[Rob Strand]

Your added 10uFd can't do much because T4 clamps that node.

No intention to argue, Paul..

The same issue came up with RG's buffer in the one of the old threads. 
https://www.diystompboxes.com/smfforum/index.php?topic=121891.0

It looks like a White follower but isn't.   I don't think we resolved why the cap is there.

[antonis]

Don't know..
Anyway, Douglas Self claims to be a working White follower..

[Rob Strand]

Don't know..
Anyway, Douglas Self claims to be a working White follower..

The 1k resistor to the diodes makes all the difference as the cap can change
the base voltage of the lower transistor.   RG's buffer doesn't have the 1k.
The impedance looking into the bias network is fairly low much makes it struggle
to work like a White follower.   That's what confused PRR and I in the old thread.

It still works, it's just a matter of the way it works.

[niektb]

thanks for all the replies guys, I find all these information utterly interesting! Following the thoughts I outlined in the other topics (to which I linked to in the first post), I wanted to experiment with different high-performance buffer types.
Lately I saw various posts of people that disliked the sound of some Opamps when driven and this reminded me of the HiFi world where people prefer Discrete over Opamps.

Sidenote: a while ago I spoke to the audio-guru Van den Hul about circuit design and he explained to me that discrete can sound a touch warmer and fatter. He also explained that overall negative feedback causes transient smearing and should be minimized as such (distortion and bandwidth should be improved as such). But I don't think this applied to Opamps too (since it's local feedback) Not sure if it's a unicorn or not but it works for him lol (he sells his products across the whole world)

Anyways back to topic! Discrete it is. I thought I did something fairly uncommon for guitar pedals but I guess the industry giants are already ahead of me XD but this is also a good thing, as it confirms that improvements are indeed to be expected! The reason I went for a JFET input is that it probably (hopefully) sounds better (than a bootstrapped BJT) when driven too hot! Replacing the source resistor gave me some very promising results which I will share with you as soon as I'm behind my computer again!

@antonis: so if T4 is there, is it still useful to add that 47R to the collector? Or would it just reduce Z-out?

I had another question! What is the optimal biasing point for the BJT stage? Vcc/2 at base or at emitter?

[niektb]

As promised, here is the new version I came up with!

With this schematic, it shows a simulated harmonic distortion of 0.0012% (two orders of magnitude lower than the previous version!)

[antonis]

@antonis: so if T4 is there, is it still useful to add that 47R to the collector? Or would it just reduce Z-out?

No, for both queries..

What is the optimal biasing point for the BJT stage? Vcc/2 at base or at emitter?

It mainly depends on signal amplitude..!!
(and secondary on next stage input impedance..)

For signals amplitude of Vp-p much lower than Vcc, it shouldn't make any difference..
When signal amplitude becomes comparable to Vcc, Emitter should be biased at Vcc/2, for equal undistorted output swing..
Actually, for a simple buffer, Emitter should be biased higher than Vcc/2, due to load current source/sink asymmetry..
(current sinking ability is reduced due to voltage dividing effect formed by Emitter resistor & Load..)
e.g. For equal values of Emitter resistor & Load, output could be go up to Vcc but only down to Vcc/4  - so Emitter should be biased at [Vcc+(Vcc/4)] / 2 (or at 5.625V for 9V Vcc.)

[Rob Strand]

With this schematic, it shows a simulated harmonic distortion of 0.0012% (two orders of magnitude lower than the previous version!)

The current source load helps a lot.   That trick is used in quite a few HiFi circuits to get low distortion.

[niektb]

[...]

What is the optimal biasing point for the BJT stage? Vcc/2 at base or at emitter?

It mainly depends on signal amplitude..!!
(and secondary on next stage input impedance..)

For signals amplitude of Vp-p much lower than Vcc, it shouldn't make any difference..
When signal amplitude becomes comparable to Vcc, Emitter should be biased at Vcc/2, for equal undistorted output swing..
Actually, for a simple buffer, Emitter should be biased higher than Vcc/2, due to load current source/sink asymmetry..
(current sinking ability is reduced due to voltage dividing effect formed by Emitter resistor & Load..)
e.g. For equal values of Emitter resistor & Load, output could be go up to Vcc but only down to Vcc/4  - so Emitter should be biased at [Vcc+(Vcc/4)] / 2 (or at 5.625V for 9V Vcc.)

But for a constant current source, how do I quantify the emitter resistance?

Also, when I bias the emitter out at 5.625V, I would have to bias the gate at roughly ~0.7V higher which is 6.325V... But this voltage now comes from the source of the FET, that is not very ideal for the output swing of the FET is it?

Futhermore, I can decrease the Harmonic Distortion even more by increasing the value of R2 (the bias resistor for the JFET gate). (10Meg gives me 0.0010%) Why is that? 2M2 is already quite high...
Could it be because of the slightly lower bias voltage?

[antonis]

But for a constant current source, how do I quantify the emitter resistance?

By implementation of Norton equivalent model (Ideal current source with a shunt resistor of very high value) or by just ignore it due to its current sinking high ability despite voltage variations..
In breef, consider the whole constant-current source configuration (T3, T4, etc) as T2 Emitter item of extremely low resistive value, hence bias Emitter at Vcc/2 point..

P.S.
The above suggestion for higher than mid-point biasing only concerned simple buffers driving loads of value comparable to Emitter resistor one..
(you don't precisely read clearly stated acceptations..)

Also, when I bias the emitter out at 5.625V, I would have to bias the gate at roughly ~0.7V higher which is 6.325V... But this voltage now comes from the source of the FET, that is not very ideal for the output swing of the FET is it?

Another (uncountable in electonics design) one compromise you'll have to make..
(it's classified under DC coupled multistage amps general category..)
You have a bounch of choices, including "sharing" distortion among individual stages or bias AC coupled individual stage with the risk of dominating overall impedance or bootstrap anything  you can imagine that should be receptive...)

P.S.
I'm defender of discrete design (for various reasons including fun.. ) only till the point of looming headache..

[niektb]

[...]

Aaah my bad, I overlooked where you said 'simple buffer'!
Funnily, with my configuration it appears that a lower bias voltage results in a lower distortion (until it hits clipping of course!)

[merlinb]

(10Meg gives me 0.0010%)

At what amplitude? What frequency? Simulated THD figures are pretty dubious at the best of times.

With two cascased followers both with CCS loads, you are rapidly running out of headroom. There's little point chasing super-low THD in a guitar box at the best of times, but if it can't even handle a full humbucker signal without clipping, what are you really gaining?

[niektb]

(10Meg gives me 0.0010%)

At what amplitude? What frequency? Simulated THD figures are pretty dubious at the best of times.

With two cascased followers both with CCS loads, you are rapidly running out of headroom. There's little point chasing super-low THD in a guitar box at the best of times, but if it can't even handle a full humbucker signal without clipping, what are you really gaining?

Aaaah that is with a 1kHz sine wave! The simulated clipping-free headroom is around 4.6V (peak-to-peak)! Should be plenty for a Humbucker I guess