Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep

[savethewhales]

Hello!

I've done some posts already regarding the construction of a phaser, for my college, based on the phase 90 by MXR. I've already studied everything and understood as much as I could.

As I am doing simulation of the circuit of the phase 90 on LTSpice, just to experiment with what I'd like to change, (circuit is shown on the figure below)



I noticed that when I'm using the 2N5486 JFET's (because Spice doesn't have 2n5952 or 2n5457), I only have room for 0.3 Volts of sweep.
What I mean by that is that, with the bias voltage at 1.1 (given that the 2N5486 is written to have -4 VGScutoff, then 1.1 minus 5.1, which is the reference voltage, equal -4 VGScutoff), I have the results shown correctly with the calculations I made (with the parallel of the resistance of the filter being 24k ohm).
Now when I change the bias voltage to 1.4 Volts, the results show this:



And when I change the bias voltage to 1.5 Volts, the results show the following:



Which in practice shows that I would have 0.3 Volt margin to oscillate the voltage in the oscillator.

This makes absolutely no sense. Could it be that these JFET's don't work for this matter? Or am I doing something wrong?  would highly appreciate any help regarding this matter.

Greetings,

Frederico Vilar

[Rob Strand]

If you doubt the JFET is working you need to verify the JFET model.

Set-up an AC input voltage of 1V driving a voltage divider with a single resistor, JFET from divider output to ground, and set the gate voltage to a known value.
Roughy,
- R1 = 200 ohm,    Vgs = 0V
- R1 = 400 ohm,    Vgs = -2V
- R1 = 1k,                Vgs = -3.2V
- R1 = 2k,               Vgs = - 3.6V

In each case the output side of the divider should be about 0.5V.  I've only roughly calculated the Vgs's since I don't know the model parameters.

The way you have the Vbias isn't 100% correct there should be a 1M resistor between the gates and Vbias.
In the real circuit the output of the LFO passes through the 3M9 (R3) then to the gates.
The bias circuit looks like a voltage source in series with a 1M resistor.

The 1M resistor allows JFETS to be biased and also allows the LFO voltage to pass to the JFETS.

The voltage swing on the LFO cap is say 1.3V p-p.   When the LFO output passes through the 3M9 it is shunted to Vbias
vias 1M resistor.    The 3M9 and the 1M form a voltage divider, so the 1.3Vp-p swing on the cap is reduced to 0.27Vp-p to the gates.
(Only rough numbers here.)

[PRR]

> 3M9

You can save zeros with "3.9Meg". (Because naked "m" is Milli.)

I'm not sure why I care how much margin to oscillate the voltage in the oscillator. In this case we would like to sweep the FET channel from >24k to a few hundred ohms. As said, this often needs trim of idle bias and sweep.

[Rob Strand]

> 3M9
You can save zeros with "3.9Meg".

For the OP, that's a peculiarity of spice

(Because naked "m" is Milli.)

Spice is a pain for that.   It originates because the original spice was as all capitals and then later it became case independent and m becomes M

When you type 3.9M in LT spice actually forces it back to 3.9m  which forces clarity to the meaning.

LT spice also has an option for 3k9 format but for MEG you have to write 3MEG9 which doesn't help the cause 
I always keep this option off since it creates habit problems when you move to other spice versions.

[Eb7+9]

... which in practice shows that I would have 0.3 Volt margin to oscillate the voltage in the oscillator.

This makes absolutely no sense.

Frederico, check out these sims I posted a while back // they show a P90 LFO swing of around 290mvpp ...

https://www.diystompboxes.com/smfforum/index.php?topic=116338.0

[savethewhales]

If you doubt the JFET is working you need to verify the JFET model.

Set-up an AC input voltage of 1V driving a voltage divider with a single resistor, JFET from divider output to ground, and set the gate voltage to a known value.
Roughy,
- R1 = 200 ohm,    Vgs = 0V
- R1 = 400 ohm,    Vgs = -2V
- R1 = 1k,                Vgs = -3.2V
- R1 = 2k,               Vgs = - 3.6V

In each case the output side of the divider should be about 0.5V.  I've only roughly calculated the Vgs's since I don't know the model parameters.

The way you have the Vbias isn't 100% correct there should be a 1M resistor between the gates and Vbias.
In the real circuit the output of the LFO passes through the 3M9 (R3) then to the gates.
The bias circuit looks like a voltage source in series with a 1M resistor.

The 1M resistor allows JFETS to be biased and also allows the LFO voltage to pass to the JFETS.

The voltage swing on the LFO cap is say 1.3V p-p.   When the LFO output passes through the 3M9 it is shunted to Vbias
vias 1M resistor.    The 3M9 and the 1M form a voltage divider, so the 1.3Vp-p swing on the cap is reduced to 0.27Vp-p to the gates.
(Only rough numbers here.)

Hello Rob! Thank you for your response!

By doing what you said, like the following image:



I am only getting around 1,375 Volt on the output (on DC op point), no matter what resistors I put.. I didn't quite understand the method you told me to test the JFET's, and if I'm doing wrong, be sure to tell me please!
Observation: This model has a -4 VGSCutoff as mentioned.

About the part of the 3M9 and the 1M resistors, I didn't use because I wanted to do the tests manually, that's why I didn't make all the refinements of the schematic. I can't seem to know how to simulate a real time frequency analyser on LTSpice, that's why I wanted to change the filters ground resistance "manually".
Anyway, I did the testing with the 1M resistor just like the schematic:



But I got no better result (at 1.5 Volt of bias, the second cancelled frequency exceeds 20k already, just like it was before).

Also, in the LFO testings I made:



We can see that the LFO Span is 1,6 Volt p-p (exact schematic of the phase 90 but the potentiometer is substituted by a "low resistance" of 10k), which is also different than 1,3 Volt p-p as you mentioned.
However besides all that I don't believe the LFO has anything to do with the "JFET volt span", because no matter what the LFO does, if the JFET changes resistance really drastically as i'm seeing it does (the one i'm using), it can't be used for more than 0.3 Vpp of LFO span anyway, so I'm guessing it depends most on the JFET case now.

I'm kinda lost but starting to understand more, so thank you.

Regards, Fred

[savethewhales]

> 3M9

You can save zeros with "3.9Meg". (Because naked "m" is Milli.)

I'm not sure why I care how much margin to oscillate the voltage in the oscillator. In this case we would like to sweep the FET channel from >24k to a few hundred ohms. As said, this often needs trim of idle bias and sweep.

Yeah I already noticed that meg in place of the M. but either way, what you mean by "this often needs trim of idle bias and sweep."?
Isn't it kinda obvious that we need to bias the voltage that goes to the gate of the FET?

... which in practice shows that I would have 0.3 Volt margin to oscillate the voltage in the oscillator.

This makes absolutely no sense.

Frederico, check out these sims I posted a while back // they show a P90 LFO swing of around 290mvpp ...

https://www.diystompboxes.com/smfforum/index.php?topic=116338.0

Eb7+9, beautiful chord it is your name.
I have the same question for you than for Rob Strand. In this case I guess the most important thing is that the JFET's itself have few span of voltage. In this matter, even if I could get a LFO with a very good voltage span, it would suit me because these specific FET's that I am simulating, don't respond well to more than 1.4 Vbias (which in practie means -3.7 VGScutoff upwards, knowing that in Spice the FET's I used are said to have cutoff at -4 VGS).

Anyway thank you very much for the information (I already saw the whole post and it will help me for sure).

Regards, Fred

[Eb7+9]

Fred, you can't do large-signal (DC and Tran) sims at the origin because the models only cover one quadrant ... that's why we don't ever see jFET VCR sims done despite being an obvious thing to try in a simulator ... I would expect small-signal (AC, noise, etc ...) sim output to be bogus in values despite the control range being respected, but that depends on how the simulator would calculate the derivative at the origin exactly in an AC sim ...

[savethewhales]

Fred, you can't do large-signal (DC and Tran) sims at the origin because the models only cover one quadrant ... that's why we don't ever see jFET VCR sims done despite being an obvious thing to try in a simulator ... I would expect small-signal (AC, noise, etc ...) sim output to be bogus in values despite the control range being respected, but that depends on how the simulator would calculate the derivative at the origin exactly in an AC sim ...

Hey Eb, yeah, thanks you very much for the explanation.. You guys nail it, i'm just new to some things. And it seems totally correct, all your explanation.
But that refers to the work of the JFET's (the output moving in real time), right?

That being the case, how can I simulate things of a phaser, just to be more clarified? I have to change the resistances manually, as i'm doing, right?

And what about that story of the 0.3 Vpp span of the JFET's? What should I be doing, you think?

Thanks, Fred

[Rob Strand]

I am only getting around 1,375 Volt on the output (on DC op point), no matter what resistors I put.. I didn't quite understand the method you told me to test the JFET's, and if I'm doing wrong, be sure to tell me please!
Observation: This model has a -4 VGSCutoff as mentioned.

Your V2 voltage needs to be negative in that test set-up.

In the phaser the JFET source is at Vref and the gate is a Vbias which is lower than Vref, which makes Vgs negative.

[Rob Strand]

I don't know what JFET model you are using but LTSpice has two models and one of them looks wrong.

The 2N5486 data sheet shows,
https://www.onsemi.com/pub/Collateral/2N5486-D.PDF

VP = -4V
Yfs = 6000uS
Idss = 12mA   ( consistent with VP and Yfs)

But LT spice library has *two* models,

.MODEL J2N5486 NJF(Beta=736.9u Betatce=-500m Rd=1 Rs=1 Lambda=9.5m Vto=-3.889 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7 Vk=243.6 Cgd=1.6p M=362.2m Pb=1 Fc=500m Cgs=2.414p Kf=5.497e-003f Af=1)

and

.model 2N5486 NJF(Is=.25p Alpha=1e-4 Vk=80 Vto=-4.0 Vtotc=-3m Beta=4.0m Lambda=10m Betatce=-.5 Rd=10 Rs=10 Cgs=4p Cgd=4p Kf=3e-17 mfg=Siliconix)

The Beta for the J2N5486 looks OK. The Beta for the 2N5486 is way too high.  It implies a Yfs of 32000uS.   Which is more like a switching JFET.

High Yfs like that is going to make the JFET look like a low resistance and it won't be much good for a phaser.

So when I use the J2N5486 model  I get an output voltage range of 514mV to 516mV.  Quite close to the expected 500mV.  (I made a few tweaks to the Vgs values since I can see the model parameters: Vgs = 0V, -2.28V, -3.25V, -3.58V.)

For the 2N5486 model I get output voltages of 175mV and 225mV, clearly too low due the low JFET resistance caused by the crapaphonic model.

[Rob Strand]

FWIW, here's the whole sim with accurate values (and even better agreement).

[Click to Enlarge]

[savethewhales]

I am only getting around 1,375 Volt on the output (on DC op point), no matter what resistors I put.. I didn't quite understand the method you told me to test the JFET's, and if I'm doing wrong, be sure to tell me please!
Observation: This model has a -4 VGSCutoff as mentioned.

Your V2 voltage needs to be negative in that test set-up.

In the phaser the JFET source is at Vref and the gate is a Vbias which is lower than Vref, which makes Vgs negative.

Ohh yeah, of course Rob, I was naive!

As I'm doing the simulation with the source inverted, I'm not getting 0.5 V in the output side :\, on the image below I show what I got (2k resistor):

[savethewhales]

I don't know what JFET model you are using but LTSpice has two models and one of them looks wrong.

The 2N5486 data sheet shows,
https://www.onsemi.com/pub/Collateral/2N5486-D.PDF

VP = -4V
Yfs = 6000uS
Idss = 12mA   ( consistent with VP and Yfs)

But LT spice library has *two* models,

.MODEL J2N5486 NJF(Beta=736.9u Betatce=-500m Rd=1 Rs=1 Lambda=9.5m Vto=-3.889 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7 Vk=243.6 Cgd=1.6p M=362.2m Pb=1 Fc=500m Cgs=2.414p Kf=5.497e-003f Af=1)

and

.model 2N5486 NJF(Is=.25p Alpha=1e-4 Vk=80 Vto=-4.0 Vtotc=-3m Beta=4.0m Lambda=10m Betatce=-.5 Rd=10 Rs=10 Cgs=4p Cgd=4p Kf=3e-17 mfg=Siliconix)

The Beta for the J2N5486 looks OK. The Beta for the 2N5486 is way too high.  It implies a Yfs of 32000uS.   Which is more like a switching JFET.

High Yfs like that is going to make the JFET look like a low resistance and it won't be much good for a phaser.

So when I use the J2N5486 model  I get an output voltage range of 514mV to 516mV.  Quite close to the expected 500mV.  (I made a few tweaks to the Vgs values since I can see the model parameters: Vgs = 0V, -2.28V, -3.25V, -3.58V.)

For the 2N5486 model I get output voltages of 175mV and 225mV, clearly too low due the low JFET resistance caused by the crapaphonic model.

Rob, now I saw this one. Thank you so much, really. I actually was using the JFET that was present in my LTSpice, I didn't even use a model. And thanks for teaching me wat is the Beta and the Yfs of the JFET's, because I didn't really know, I was just focused on the VGScuttof as you may imagine.

I did the simulation with the "new model" with the following circuit and parameters:



And I got 644 mV to 153 mV depending on the resistor value I tested...

Now when using it in the phaser, it responds waaay better!! I have a voltage span of 1.8 Volt now!! The only thing is i'm getting -14 dB in the gain, any thoughts on that anybody?

**UPDATE** When I put a higher input, it gives me more gain, like ?!?!? Does that make any sense? For me no actually

Greetings, Fred

[Rob Strand]

I didn't even use a model. And thanks for teaching me wat is the Beta and the Yfs of the JFET's, because I didn't really know, I was just focused on the VGScuttof as you may imagine.
I did the simulation with the "new model" with the following circuit and parameters:

You were using model just that the model is in the LTSpice's library.    You should find the file of JFET models,

  {your LTSPICE folder}\lib\cmp\standard.jft

You can open that file up as text and see the models.   You can also add models.

You should be able to just change the part name on the schematic from 2N5486 to J2N5486, as you have already done, without putting the model down on the schematic.   However, the models supplied in LT spice seem to vary from version to version so if your sim barfs then you might actually *need* to plop the model down on the schematic.

The only thing is i'm getting -14 dB in the gain, any thoughts on that anybody?

Changing the JFET shouldn't affect the gain.  Maybe the DC biasing has got screwed up somewhere.

After a simulation, click on the schematic area, then move the cursor over the circuit wires.  At the bottom of the LTspice window you should be able to see some numbers showing the DC voltages.   Make sure they all look OK:  about Vcc/2 on the opamps.  check the transistor as well, the collector should sit at about 2.5V.

[savethewhales]

I didn't even use a model. And thanks for teaching me wat is the Beta and the Yfs of the JFET's, because I didn't really know, I was just focused on the VGScuttof as you may imagine.
I did the simulation with the "new model" with the following circuit and parameters:

You were using model just that the model is in the LTSpice's library.    You should find the file of JFET models,

  {your LTSPICE folder}\lib\cmp\standard.jft

You can open that file up as text and see the models.   You can also add models.

You should be able to just change the part name on the schematic from 2N5486 to J2N5486, as you have already done, without putting the model down on the schematic.   However, the models supplied in LT spice seem to vary from version to version so if your sim barfs then you might actually *need* to plot the model down on the schematic.

The only thing is i'm getting -14 dB in the gain, any thoughts on that anybody?

Changing the JFET shouldn't affect the gain.  Maybe the DC biasing has got screwed up somewhere.

After a simulation, click on the schematic area, then move the cursor over the circuit wires.  At the bottom of the LTspice window you should be able to see some numbers showing the DC voltages.   Make sure they all look OK:  about Vcc/2 on the opamps.  check the transistor as well, the collector should sit at about 2.5V.

Hi Rob,

You are helping me a ton, really. I just added the model of the JFET to the LTSpice library and erased the model from the schematic and it worked!!!

Unhappily, the collector gives 3.27 V DC, for some reason. The op-amp gives 9V in the positive and 0 V in the negative, as i'm using a 9V baterry to power up.

Greetings, Fred

[Rob Strand]

I just added the model of the JFET to the LTSpice library and erased the model from the schematic and it worked!!!

OK cool. 

Unhappily, the collector gives 3.27 V DC, for some reason.

That's not enough to cause the -14dB.

A small detail is the Vref is actually about 4.8V on the real circuit.   Even though the zener is 5.1V, the zener is operating at a low current and that causes the zener voltage to drop to 4.8V.    If you make that change it will drop the collector voltage down to 2.97V.
The difference from 2.5 to 2.9V could be caused by the model [the reason is the transistor is operating at low current so the Vbe is 0.59V not the assumed 0.65V.]    I can't remember the exact voltage on the real unit.

I think the real problem is your signal source is 0.1V AC.   dB in spice is referenced to 1V  so you are only putting in a -20dBV signal.  The summing from the mixer will give 6dB gain so that adds up to -14dBV.     In operation the peaks and notches of the phaser will averaged out to remove the 6dB static gain.

All you need to change is your AC voltage, make it 1V.    FWIW,  the AC voltage levels won't cause any clipping in spice.  It's a small-signal mode.  You can input 1000V into a 9V circuit and the performance will be exactly the same as 0.1V or 1V.   All the AC level does is change the scaling of the  numbers.    For eyeballing gains a 1V AC input is by far the most convenient number.     When you do transient simulations with a SINE source, that's a whole different ball-game, it will show clipping so you need realistic voltage levels.
 

[savethewhales]

I just added the model of the JFET to the LTSpice library and erased the model from the schematic and it worked!!!

OK cool. 

Unhappily, the collector gives 3.27 V DC, for some reason.

That's not enough to cause the -14dB.

A small detail is the Vref is actually about 4.8V on the real circuit.   Even though the zener is 5.1V, the zener is operating at a low current and that causes the zener voltage to drop to 4.8V.    If you make that change it will drop the collector voltage down to 2.97V.
The difference from 2.5 to 2.9V could be caused by the model [the reason is the transistor is operating at low current so the Vbe is 0.59V not the assumed 0.65V.]    I can't remember the exact voltage on the real unit.

I think the real problem is your signal source is 0.1V AC.   dB in spice is referenced to 1V  so you are only putting in a -20dBV signal.  The summing from the mixer will give 6dB gain so that adds up to -14dBV.     In operation the peaks and notches of the phaser will averaged out to remove the 6dB static gain.

All you need to change is your AC voltage, make it 1V.    FWIW,  the AC voltage levels won't cause any clipping in spice.  It's a small-signal mode.  You can input 1000V into a 9V circuit and the performance will be exactly the same as 0.1V or 1V.   All the AC level does is change the scaling of the  numbers.    For eyeballing gains a 1V AC input is by far the most convenient number.     When you do transient simulations with a SINE source, that's a whole different ball-game, it will show clipping so you need realistic voltage levels.

It's reasonable that those changes might be for the low current and the model/components used. I just fear that the simulations might be too diferrent in real life, that would actually suck.

I think the real problem is your signal source is 0.1V AC.   dB in spice is referenced to 1V  so you are only putting in a -20dBV signal.  The summing from the mixer will give 6dB gain so that adds up to -14dBV.     In operation the peaks and notches of the phaser will averaged out to remove the 6dB static gain.
 

So, as I mentined before, I was just testing the voltages on the input, and as a standar I was actually using 1Volt so you're right. It gives a bettwr result. It's just it shouldn't be different response fpr diferrent input voltages, I guess. Why would I have more gain on higher voltages?

All you need to change is your AC voltage, make it 1V.    FWIW,  the AC voltage levels won't cause any clipping in spice.  It's a small-signal mode.  You can input 1000V into a 9V circuit and the performance will be exactly the same as 0.1V or 1V.   All the AC level does is change the scaling of the  numbers.    For eyeballing gains a 1V AC input is by far the most convenient number.     When you do transient simulations with a SINE source, that's a whole different ball-game, it will show clipping so you need realistic voltage levels.

I did 1V and got +- 5dB of gain in the end of the chain. And thanks for the insight on the working of the simulations. That could help me a ton. I actually had problems one time with amplitude response (on 3 different softwares I couldn't do it with an class AB amplifier if I'm not mistaken, and my colleagues too).

Anyway, with a voltage divider I must be able to have 0 gain on the output, right? Or do you recommend me trying only when I test it physically?

Greetings, Fred

[Rob Strand]

It's reasonable that those changes might be for the low current and the model/components used. I just fear that the simulations might be too diferrent in real life, that would actually suck.

The low current thing is a real effect.   For transistors the spice models are quite good and can represent real life.  However just like you found with the two JFET models, the spice model for a given part might not be trustworthy unless you verify it - which takes extra effort.

For the zener the low voltage a low currents is a known characteristic of zeners.   People have measured the voltage on the MXR pedals over the years and it does come out around 4.8V.

There's no zener model in spice and zener models are the least trustworthy.   Many won't show enough drop in voltage at low currents.

If you take your simulation you have a solid Vbias.    Physically that's not realistic but it's often a good strategy.   To make the simulation better you would use the human knowledge that the zener voltage is 4.8V and not the 5.1V on the label.    The simulation would represent reality quite well and you don't have to deal with the messy problem of having an exact zener model with a 10k resistor to 9V, which is going to give you 4.8V anyway!

In general you have to have a good level of mistrust in spice.    The models are rarely good.   Different models from different manufacturers vary.    I've got about 5 models for LM741 opamps and only one or two are even close to reality.    For AC simulations, I don't even use real models I use something like LTspice's model "opamp";  IIRC the supplied model had a bug.  For .TRANS you need on opamp model with PSU rails.

So, as I mentined before, I was just testing the voltages on the input, and as a standar I was actually using 1Volt so you're right. It gives a bettwr result. It's just it shouldn't be different response fpr diferrent input voltages, I guess. Why would I have more gain on higher voltages?

The key thing is it doesn't plot gain.   It plots dBV, which is defined as

    dbV = 20*log10( V  / 1V)  = 20*log10(V)

It is simply a conversion of volts to dB without any consideration of the input source level.   

For gain you need,

     dB gain = 20*log10(Vout/Vin).   

So the two only agree when Vin is 1V.

You can actually plot expressions in LTspice and other Spice versions, so if you wanted you could plot the AC analysis expression,

      Vout/Vin

and then plot would show  dB gain = 20*log10(Vout/Vin).

In some versions of spice the variable expressions are already in dB and to get gain you can type something like Vout - Vin, which is actually dB(Vout) - dB(Vin).

I did 1V and got +- 5dB of gain in the end of the chain. And thanks for the insight on the working of the simulations. That could help me a ton. I actually had problems one time with amplitude response (on 3 different softwares I couldn't do it with an class AB amplifier if I'm not mistaken, and my colleagues too).

Unfortunately with spice sims it only takes one thing to go wrong and it all falls in a heap; like not plugging in the power on your breadboard.   Small differences between packages can confuse things.    I often start with simple dumb circuits where you already know the answer, then run a lot of sims and play with the waveform plotter.   No doubt you will find some things which don't make sense.  Good to keep notes.

Anyway, with a voltage divider I must be able to have 0 gain on the output, right? Or do you recommend me trying only when I test it physically?

I'm not sure what you are asking here.

[PRR]

...the zener voltage is 4.8V and not the 5.1V on the label.  ... problem of having an exact zener model with a 10k resistor to 9V, which is going to give you 4.8V anyway!

Yes, don't trust SPICE at all, or its models.

The "sag" of Vz at low currents is 'normal' of course; philosophically it must go to zero at zero current, and there may be no "magic current" where it jumps-up to rated value.

Curious, I plotted the one Zener in my spice. (Yes, a 4.7V breakover is different from a >7V breakover.) At 0.4mA (9V through 10K) it reads a little low, though not as low as is reported for P90s.