Help with the simulation of Phase 90 on LTSpice!!! JFET's giving 0.3 Volt sweep

[savethewhales]

Instead of that mambo jambo, I've managed to have a DC offset with a capacitor of a big value, and a resistor connected in one side to the capacitor and other side to the new "DC offset" wanted.
I guess I'm done with the LFO circuit..

Anything that I must keep an eye on?

[Rob Strand]

Why would I want a DC level when the depth pot is at minimum?

When the Depth pot is on minimum the circuit has to do *something*.   The notches will be fixed so you want to put them in a place that makes the Depth control sound the best of its range of adjustment.

The BF2 has the Manual pot to put that decision in the hands of the user.  (Partly because the range of delays is so wide on a flanger).

Ok, this is where I get confused.. All I want is to set the DC level (which was around 4.8V) to center the triangle at 3.8 V.. How can I do it? Or I change the time constant in the circuit I done, or I do a DC couple? Is that it?

When you AC couple it will always have a time constant.    You just have to live with it.   If you want to get rid of it then DC coupling is the way to go.

Instead of that mambo jambo, I've managed to have a DC offset with a capacitor of a big value, and a resistor connected in one side to the capacitor and other side to the new "DC offset" wanted.
I guess I'm done with the LFO circuit..

That should work fine.  The JFET gates are high impedance so you don't gain anything by adding the buffer.

Anything that I must keep an eye on?

Only, something to think about.

The way you have the depth varies how widely the sweep is in terms of how far the notches move in frequency.    Another type of depth is to reduce the level from the output of the all-pass filter bank.   What that does is change the depth of the notches and leaves the sweep "width" the same.  The two methods sound different.

[savethewhales]

When the Depth pot is on minimum the circuit has to do *something*.   The notches will be fixed so you want to put them in a place that makes the Depth control sound the best of its range of adjustment.

The BF2 has the Manual pot to put that decision in the hands of the user.  (Partly because the range of delays is so wide on a flanger).

Okay I think I understand. In my case when my pot is on minimum, the triangle will almost be DC, so yeah there will be a notch but ordinary people (or even trained) will not listen to it. So it makes sense. How they do it is another story (which maybe I would like to learn in a near future, maybe not now).

That should work fine.  The JFET gates are high impedance so you don't gain anything by adding the buffer.

Of course.. It's just I'm kinda trying to go fast on this and the way that I found to do a DC offset was that one, but I ended up stuck there for hours and found the way that is now in my circuit, after searching lots of places on the web.

Only, something to think about.

The way you have the depth varies how widely the sweep is in terms of how far the notches move in frequency.    Another type of depth is to reduce the level from the output of the all-pass filter bank.   What that does is change the depth of the notches and leaves the sweep "width" the same.  The two methods sound different.

That is very true and it's something I've been thinking. Anyway I will try do to both on my pedal. Btw, the boss schematics use what depth ? the depth of the notches?

[Rob Strand]

That is very true and it's something I've been thinking. Anyway I will try do to both on my pedal. Btw, the boss schematics use what depth ? the depth of the notches?

On a flanger (or chorus or delay) the Depth as you have it might be called Width, Range, and Depth.    The alternate form of adjusting depth of the notches is often called "level" or "mix" (possibly depth on some units) because it adjusts the level of the delayed signal.

[savethewhales]

On a flanger (or chorus or delay) the Depth as you have it might be called Width, Range, and Depth.    The alternate form of adjusting depth of the notches is often called "level" or "mix" (possibly depth on some units) because it adjusts the level of the delayed signal.

Right. Yeah it makes sense to call it mix. I'll try it too.

[savethewhales]

So with the last LFO circuit that I put above, I'm having problems in the tests...

And by curiosity I went to do a simulation to see how it behaves in 100 seconds:




What is happening? I thought it would behave good with that 100uF cap..

[savethewhales]

Well it's the end of my tests and I have some points to ask.

First, let me say I've tested this circuit:



Now I wanted to say 2 things which happened to me:

- the circuit overall was taking like 1 min to stabilize (when I turned it on, it would stay at a higher voltage, and then 60 seconds later the voltage would drop a bit to the desired point), even though the Voltage difference isn't very big.
I have no idea what is happening but it "agrees" with the simulation that I posted above. Maybe it's what Rob said about the time constant, but I wouldn't know how to take it off :/..

- when I messed with a potentiometer far ahead in the circuit, it was slightly affecting the previous parts of the circuit. I noticed that when messing with the depth while seeing the stage before that on the osciloscope input.
I may have an idea of why this is happening, and I'm guessing it's a voltage divider that happens when certain positions of the trimmers/potentiometers are reached.
IF it's that, the way to go would be isolate one part from the other, namely with an op-amp, right?

Maybe I should be posting this elsewhere/starting a new thread.. Please let me know if that's the case.

Thanks in advance.

[Rob Strand]

I have no idea what is happening but it "agrees" with the simulation that I posted above. Maybe it's what Rob said about the time constant, but I wouldn't know how to take it off :/..

When you power-up a circuit which has different DC voltages each side of a cap the cap must charge-up through whatever circuit resistances it can until a steady-state is reached.

If you think about JFET matching we aimed for better than 50mV matching.  That means that circuit needs to stabilize to within say 50mV/2 = 25mV in order to have no noticeable effect.   If you have a cap with 2V difference each side the cap voltage needs to stabilize to within 25mV.    A cap charging to 2V will reach 2V-25mV = 1.975V in about 4.4 time constants.  Your circuit has R=100k and C=100uF, so time constant = RC = 10 seconds.  So we are looking at 4.4 * 10 seconds = 44 seconds to stabilize.    About the 1 min you are seeing.   All rough numbers as the initial 25mV is only a rough estimate.

When you introduce the AC coupling the start-up timing constant comes with it.   So the options are:
- reduce the time constant, ie. smaller coupling cap.   You can only go so far here as a small cap will start affecting the LFO waveshape at low speeds.
- charge the cap up quicker on power up.   Not so easy to do in practice.
- use DC coupling

when I messed with a potentiometer far ahead in the circuit, it was slightly affecting the previous parts of the circuit. I noticed that when messing with the depth while seeing the stage before that on the osciloscope input.
I may have an idea of why this is happening, and I'm guessing it's a voltage divider that happens when certain positions of the trimmers/potentiometers are reached.
IF it's that, the way to go would be isolate one part from the other, namely with an op-amp, right?

It depends on the specific problem.    An opamp might solve it but, for example, you might be able to just use a higher value pot.

Maybe I should be posting this elsewhere/starting a new thread.. Please let me know if that's the case.

Up to you.

[savethewhales]

When you power-up a circuit which has different DC voltages each side of a cap the cap must charge-up through whatever circuit resistances it can until a steady-state is reached...

... use DC coupling

Hmm ok! My cap has aproximately a 1V difference as far as I am aware (4.83 Volt to 3.75 V) but maybe i'm wrong.

You're totally right about the cap values and lower speeds. I actually simulated with way lower caps and with a LFO frequency of 0.3 Hz, the wave would be distorted, and it makes sense actually (the high pass was higher than 1.59 Hz).

In the end I came to the conclusion that a 10uF cap plus a 100k resistance was enough, and it was giving me minus than 5 seconds of stabilization. Very good for me.

(how do I do DC coupling? Just for interest).

It depends on the specific problem.    An opamp might solve it but, for example, you might be able to just use a higher value pot.

Unfortunately I only have 500k pots and 1M pots, but I'm starting to think that 18k/100k divider is the problem..

Anyway to solve the problem with op amps, should I use them as buffers?

[savethewhales]

I have one punctual question:



Within this LFO circuit, in the far right, there's, in red, the Vgate. The Vgate is the LFO voltage which is going directly to the jFET gates.
I'm thinking that the 100k ground resistor could make a divider with the FET's, or am I wrong? If i'm right, do I have to do anything in order for it not to happen?

Thanks in advance.

[PRR]

....100k ground resistor could make a divider with the FET's,

"Ground resistor"?

But yes. Everything is a voltage divider. What is the resistance of one/few JFET Gates?

[savethewhales]

"Ground resistor"?

But yes. Everything is a voltage divider. What is the resistance of one/few JFET Gates?

You're right.. Vbias resistor.

How can I measure that?

I read that the common sense is to assume JFET input impedance of 1Mega ohm.. IF that's the case, I would have to put a fat resistor at the output of the LFO, just like the Phase 90 one, right? 

[PRR]

> assume JFET input impedance of 1Mega ohm..

That would suck. Easily 100Megs. Almost never something to worry about.
https://en.wikipedia.org/wiki/JFET

[savethewhales]

> assume JFET input impedance of 1Mega ohm..

That would suck. Easily 100Megs. Almost never something to worry about.
https://en.wikipedia.org/wiki/JFET

Alright thanks PRR!!

[savethewhales]

Hello again guys

I am already testing on a pcb, and for this LFO circuit:



When I turn the depth pot, it is shifting my DC also, which is something I didn't want and didn't design.. What could be causing this? I thought the buffer op-amps would solve this kind of problem but in the way this circuit is, it's not solving..

By the way, the only thing which I wanted to shift my DC is the "Vbias", which is at the end of my LFO circuit and comes from this part of the circuit:



Any kind of help would be very appreciated, and thanks in advance!

[savethewhales]

Another thing,

As I was going to do tests to my circuit, I was naive because I didn't realize that I had to know what the output wave should look like. I just came to college and started connecting cables.

Now I have a transient response, seen on the oscilloscope, but I don't actually know what should I be seeing coming out of a Phasing circuit, (hope I'm being clear here). When I did transient simulations, with the LFO, I got this in the output of my pedal:



Is this what I should be expecting? (No I haven't got this in the output yet, on my oscilloscope)

Well I guess I did it now. This is what I got on the oscilloscope:

(blue wave - with feedback on)



(blue wave - feedback off - different frequency than the above)

[savethewhales]

Well, I managed to solve the last two problems of the last two posts I did (should I delete them?)

The thing is: The circuit worked perfectly (after, of course having mistakes like soldering wrongly a potentiometer, and other problems which were solved later.)

These are images of what I was seeing on the oscilloscope (Phaser circuit - input yellow vs output blue):

(if I'm not mistaken)
Everything on max (range of the LFO, ressonance, mix/ammount and speed of the LFO):


Maybe everything on minimum:


I don't kknow exactly the settings:


More zoom (yes bad connections):


LFO behaviour:



With the speed on maximum it behaves like this (which I don't care too much because it isn't even noticeable auditively, I suppose - it's 9 Hz of frequency):


All of this is just to say that the circuit works, everything seems fine for now. Next step is getting a "box" for it and delivering the right power, with true bypass, battery and 9V power switch, LED, which I will do when I have my hands on the "box". I already know how I will do the connections, and hopefully everything will go right.

So thank you soooo much to all of you who responded me here during the time I was here making questions.

Without you this would be absolutely nothing.

[savethewhales]

I'm writing the project now and I wanted to explain some things I've done with the pedal circuit, however, there's this part of the circuit, which is the LFO:



And the LFO is based on a non inverting Schmitt Trigger followed by an integrator, but I don't know how to explain the values I got.. All I did was to basically learn the basic which was that the two positive feedback resistances established Upper and lower thresholds and I went on to experiment to get a good result by seeing the triangle on the oscilloscope. I don't seem to be able to get there by doing reverse calculations..

These are the sims taken directly from the circuit shown:



Where the square is the output of the schmitt trigger and the Vastable is the output of the integrator (triangle).

By searching on the web I came to discover that the equations for the Upper and Lower thresholds of the Schmitt -Trigger are
- VUT(voltage upper threshold)=(1+47k/270k)Vref+Vcc*47k/270k
- VLT(Voltage lower threshold)=(1+47k/270k)Vref+(-Vcc)*47k/270k

But when I go and calculate it, the values don't actually go right with the simulations I did on Spice... Can somebody help me please? Thank you very much in advance.

[PRR]

I don't know why it is not cooperating, but...

What do U11 U12 do ?

If R38 e R39 is made a 10k pot, why does it need U10?

C11 and C12 different values opposite directions?

R32??

It does not have to be this complicated.

[Rob Strand]

I'm assuming you are only interested in the oscillator around U7 and U8.
Also the sims are the signals at those IC's.  Yes?

So I started with these equations

(Vref - VLO) /47k =( VOH -Vref)/270k
(VHI - Vref) /47k =(Vref -VOL)/270k

Which simplify to,
VLO = (1 + 47k/270k)*Vref - VOH * 47k/270k
VHI = (1 + 47k/270k)*Vref  - VOL * 47k/270k

The Schmitt input thresholds are VLO and VHI.
The opamp VOH and VOL are the output levels at the point marked SQUARE, the output of U7.

Your equations use +/-Vcc but in reality VOH is about +Vcc-1.5 and VOL is -Vcc + 1.5V, as the opamp doesn't swing fully to the rails.

So here's where I get confused.   On your sim U7 is powered from +/- Vcc  so you would expect U7 to swing +/-Vcc (or the more accurate levels I just quoted).   However your U7 is swinging 1.5V to 7.5V.   It looks like U7 is powered from 0V and Vcc.

So that's definitely a source of a problem.  I can't see why on your sim.  Maybe probe the DC voltages on the power pins of U7 or check the connections on the schematic.    See if you can work out why U7 isn't swing to the correct voltage.


Also I couldn't see what voltage you used for Vref on the schematic.