Voltage divider on Rockman Compressor schematic

[Vivek]

In the Rockman Patent, Tom used a voltage divider across the integration cap, to scale the cap voltage and to discharge the integration cap.

R106 went to ground.


However in the actual schematics, R106 goes to Source rather than ground.

I'm sure there is a very good reason for that. I dont know the reason but my best guess is that maybe involving Rds into the voltage divider equation linearises the response somehow

Please teach me why R106 goes to Source and not to ground.

Thanks !!!

[iainpunk]

not sure about any of it but i can think of 2 reasons:

first thought: i'd suspect to never fully deplete the capacitor charge, to leave in a little bit so it triggers faster, or always keeps being triggered a little bit to minimize turn-on artifacts on every attack when playing staccato.

2nd thought: maybe by feeding a little bit of signal to the gate, it will minimize the distortion on the positive cycle halves.

i hope my ideas were wrong and i learn something new today, but i'd be glad if i'm right too.
cheers, Iain

[Vivek]

not sure about any of it but i can think of 2 reasons:

first thought: i'd suspect to never fully deplete the capacitor charge, to leave in a little bit so it triggers faster, or always keeps being triggered a little bit to minimize turn-on artifacts on every attack when playing staccato.

Wouldn't the cap discharge totally anyway ? When Cap has less charge, gate has less voltage, FET is more open ie low resistance

2nd thought: maybe by feeding a little bit of signal to the gate, it will minimize the distortion on the positive cycle halves.

i hope my ideas were wrong and i learn something new today, but i'd be glad if i'm right too.
cheers, Iain

I dont understand this, But some other DIYer did say something similar about Rds varying with Vds (which is the Audio signal) and R106 needs to go to source to counter that. Please help me step by step to understand why would there be distortion if R106 went to ground ? Why only distortion on + half cycles ?


Thanks !!!

[PRR]

> R106 goes to Source rather than ground.

https://www.vishay.com/docs/70598/70598.pdf  page 6

[iainpunk]

not sure about any of it but i can think of 2 reasons:

first thought: i'd suspect to never fully deplete the capacitor charge, to leave in a little bit so it triggers faster, or always keeps being triggered a little bit to minimize turn-on artifacts on every attack when playing staccato.

Wouldn't the cap discharge totally anyway ? When Cap has less charge, gate has less voltage, FET is more open ie low resistance

i just realized that the diode D117 to the R175 and R176 node keeps the cap charged a little bit anyways, so that idea is off the table.
what this leads me to believe is that they always want some Bias current flowing, through that diode and resistor set.

2nd thought: maybe by feeding a little bit of signal to the gate, it will minimize the distortion on the positive cycle halves.

i hope my ideas were wrong and i learn something new today, but i'd be glad if i'm right too.
cheers, Iain

I dont understand this, But some other DIYer did say something similar about Rds varying with Vds (which is the Audio signal) and R106 needs to go to source to counter that. Please help me step by step to understand why would there be distortion if R106 went to ground ? Why only distortion on + half cycles ?

sorry, yes, both cycle halves will be distorted, but the positive half will be squashed and the negative halve will be elongated slightly, the elongation is way less present than the squashing because the Vds to Rds effect is quite small
Jfets are nearly symmetrical, if there wasn't a resistor there, at the positive half of the wave, the drain and source ''switch places'' because the current runs through the other direction, and there is AC signal at what now becomes the source, if Vgs changes with that signal, the resistance it represents changes. having the current run through it the right direction, always, makes the D and S not switch places, so not changing the Vgs.

cheers, Iain

[Vivek]

> R106 goes to Source rather than ground.

https://www.vishay.com/docs/70598/70598.pdf  page 6

Wow, that paper is very pertinent !!!

Thank you !!!

[Vivek]

In the Vishay paper, they show that the two resistors to linearise the FET are equal in value


however in Tom's schematics, they are slightly lopsided

For example 6.8 Megs and 5.1 megs

And there is a note that these resistors are factory chosen to suit the particular physical FET in that board.

Why ?


Any reason why the resistors are not the same ?

[iainpunk]

vishay's paper uses a certain Jfet, that is not real, but has average values. the real Jfets have to have a different voltage ratio.

cheers

[Rob Strand]

Any reason why the resistors are not the same ?

I think you get that the resistors are for linearization.   You can prove the equal value thing with the Triode mode equations.   The assumption is the equations represent reality.  The equations assume an exact square-law characteristic.  The classical JFET equations  have two forms, one for Triode/resistance mode and the other for saturation/amplifier mode.   You switch between the two depending on the device voltages.    In reality there will be an overlap region where the equations don't quite work.   Spice switches between the two equations but you could try a large AC signal which approached the saturation region then try to choose the resistors to linearize it and see how the resistor ratio pans out.    It's not an exact answer only a guide and the resistor values might only be valid at that drive level.  No doubt the parts were chosen at a given drive level.   Low VP parts will show-up problems at lower voltages.  I know I've played with this in the past but the result isn't in my head.

EDIT:
FYI, based on LTspice with a large excitation it's looking like equal resistors are better.   Unfortunately I don't have the old spice software running to check my old files.

[PRR]

If we assume the signal voltage is zero, we do not need the trim.

We want large signal for relatively less hiss. We want signal a large fraction of a Volt.

The gain control bias is a volt or so.

:. Therefore the gain control bias (as has been said) varies over the signal waveform. Distortion.

The insight is that we really want to reference bias, not to D or S, but to the point MID-way between D and S.

While equal-value may be convenient, it has also been convenient to take gain of 10 in the amplifier and loss of 10:1 in the divider. Making the same cancellation with less side-effects.

I have no idea how they came to 69:51, but note the NOTE that this is "selected". Which is hard to believe in a profitable pedal, but you can't believe everything you read somewhere.

[Rob Strand]

While equal-value may be convenient, it has also been convenient to take gain of 10 in the amplifier and loss of 10:1 in the divider. Making the same cancellation with less side-effects.

Phil Allison's limiter is an example of that.   (He also uses C3 to tweak the HF distortion.)

https://en.postila.io/post/56350442

(In effect, still like equal resistors.)

[Vivek]

If the bias resistors are factory chosen,

What parameter are they trying to optimize ?

THD ?

Differences in Vgsoff of different FETs ?

[Vivek]

https://books.google.ae/books?id=EEcemABAU44C&pg=PA139&redir_esc=y&hl=en#v=onepage&q&f=false

More info re FET as variable resistor

[Rob Strand]

This note is one of the better documents on the topic.
AN-129, A Linear Multiple Gain-Controlled Amplifier, National Semiconductors; Jim Sherwin 1975.

Go to,
https://the-eye.eu/public/Books/Electronic%20Archive/NatSemiFetDatabook1977_text.pdf

Check out PDF pages 252 to 259 (doc pages 6-39 to 6-46)

The document is very hard to find, it's hidden in the 1977 JFET Databook
and only appears in the 1980 version of the Linear Applications Handbook;
the least available version on the web.

What parameter are they trying to optimize ?

THD ?

Highly likely to be THD at some specified level,  perhaps the level they publish their specs  .
(For LTspice that turns out to be equal resistors.)

[Rob Strand]

FYI, Fairchild reproduced the National Semiconductor Application Note AN-129,  then ON-Semiconductors took over Fairchild,

https://www.onsemi.com/pub/Collateral/AN-6603.pdf

(Nicer print and cleaner pics but I can't guarantee the newer version is error free like the old one!)

[Vivek]

Thank you Rob Strand, PRR, iainpunk for showing me the light on this peculiar application of feedback on a FET to linearise the Rds versus Vgs and try and make Rds independent of Vds.

I am indebted !!!